Sorting a vector in VHDL

Question

I was trying to sort a vector for example if the input is 101010 the output would be 111000. Every time when I am trying to simulate the code, my output is always all zeros.

I am posting my code for your reference. If I am missing something or if there is any better way to implement this please let me know

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity num_ones_for is
    Port ( A : in  STD_LOGIC_VECTOR (15 downto 0);
           A_S : out  STD_LOGIC_VECTOR (15 downto 0));
end num_ones_for;

architecture Behavioral of num_ones_for is
function sort_binary ( ones :unsigned;a : std_logic_vector) return std_logic_vector is
    variable A1: std_logic_vector ( 15 downto 0) := (others =>'0') ;
    begin
    for i in 15 to(15 - to_integer(ones)) loop
     A1(i) := '1';
    end loop;
    return A1;
    end function sort_binary;
signal ones : unsigned (4 downto 0);
begin

process(A)
variable count : unsigned(4 downto 0) := "00000";
begin

count := "00000";   --initialize count variable.
    for i in 0 to 15 loop   --for all the bits.
        count := count + ("0000" & A(i));   --Add the bit to the count.
    end loop;
    ones <= count;    --assign the count to output.
end process;
A_S <= sort_binary(ones =>ones,a =>A);

end Behavioral;

enter image description here

You have signal ones declared in the architecture statement part instead of in the architecture declarative part. Variable count is declared in the process statement sequence of statements instead of the the process statement declarative part. Both are on the wrong side of the preceding respective reserved words `begin`. There's an error in the function body's for loop parameter range. The type of right bounds ones is not compatible with left bounds literal 0. Convert ones to integer: `for i in 0 to to_integer(ones) loop` — , May 09 '21 at 11:42
`for i in 15 to(15 - to_integer(ones)) loop` unless the integer value of ones is 0 this represents a null range. The sequence of statements in a loop statement with a null range won't be executed. The right bounds expression doesn't need parentheses and the direction should be downto. — , May 09 '21 at 13:43

score 1 · Accepted Answer · answered May 09 '21 at 23:16

At last, I resolved most of the errors and changed the logic of the code a bit. If anyone wants to code the same type of VHDL code in the future, could refer to my code. If there is any better way to do solve this please let me know always happy to learn. Thanks

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity num_ones_for is
    Port ( A : in  STD_LOGIC_VECTOR (15 downto 0);
           A_S : out  STD_LOGIC_VECTOR (15 downto 0));
end num_ones_for;

architecture Behavioral of num_ones_for is
function sort_binary ( ones :unsigned;a : std_logic_vector) return std_logic_vector is
    variable A1: std_logic_vector ( 15 downto 0) := (others =>'0') ;
    begin
    for i in 0 to 15 loop
    if i >(15- ones) then
     A1(i) := '1';
     else
     next;
     end if;
    end loop;
    return A1;
    end function sort_binary;
signal ones : unsigned (4 downto 0);
begin

process(A)
variable count : unsigned(4 downto 0);
begin

count := "00000";   --initialize count variable.
    for i in 0 to 15 loop   --for all the bits.
        count := count + ("0000" & A(i));   --Add the bit to the count.
    end loop;
    ones <= count;    --assign the count to output.
end process;
A_S <= sort_binary(ones =>ones,a =>A);

end Behavioral;

enter image description here

Sorting a vector in VHDL

1 Answers1