4-bit adder subtractor Verilog code errors

Question

I am trying to do a 4-bit adder subtractor in Verilog code, but there is some kind of problem in my code that I couldn't figure out. I'm not sure if the testbench or the Verilog is wrong. Can someone please help me with it? Also, when I try to simulate it, it gives Loading Errors.

My Verilog code:

module addsubparameter (A, B, OP, C_out, Sum);

input A,B;
input OP;
output C_out;
output Sum;

wire C_out, Sum;
reg assigning;

always@(OP)
begin
if (OP == 0)
    assigning = A + B + OP;
else
    assigning = A + (~B + 1) + OP;
end

assign {C_out, Sum} = assigning;

endmodule

module adder (a, b, op, cout, sum);
parameter size = 4 ;

input [3:0] a, b;
output [3:0] sum;

input op;
output cout;
wire [2:0] c;

genvar i;
generate
for (i = 0; i < size; i = i + 1) begin: adder
    if (i == 0)
        addsubparameter (a[i], b[i], op, sum[i], c[i]);
    else if (i == 3) 
        addsubparameter (a[i], b[i], c[i-1], cout, sum[i]);
    else
        addsubparameter (a[i], b[i], c[i-1], sum[i], c[i]);
end 
endgenerate
endmodule

And this is my testbench:

module addsub_tb();

reg [3:0] a;
reg [3:0] b;
reg op;

wire [3:0] sum;
wire cout;

adder DUT (a,b,op,sum,cout);

initial begin
    a = 4'b1010; b = 4'b1100; op = 1'b0; #100;
    a = 4'b1111; b = 4'b1011; op = 1'b1; #100;
    a = 4'b1010; b = 4'b1010; op = 1'b0; #100;
end
      
endmodule

score 2 · Accepted Answer · answered May 01 '21 at 16:04

Your simulator should generate error and/or warning messages because you have syntax errors. If it does not, sign up for a free account on edaplayground, where you will have access to multiple simulators which will produce helpful messages.

You need to add instance names. For example, I added i0 in the line below:

    addsubparameter i0 (a[i], b[i], op, sum[i], c[i]);

You have port connection width mismatches, and these indicate connection errors. This is a common type of error when you use connections by position. You mistakenly connected the sum signal to the cout port, and vice versa. You should use connections by name instead. For example, change:

adder DUT (a,b,op,sum,cout);

to:

adder dut (
    .a     (a),
    .b     (b),
    .op    (op),
    .cout  (cout),
    .sum   (sum)
);

Use this coding style for all your instances.

You won't get a simulation warning, but you might get a synthesis warnings about an incomplete sensitivity list. Change:

always@(OP)

to:

always @*

4-bit adder subtractor Verilog code errors

1 Answers1