Change value of internal signals while running simulation

Question

I would like to know how I can change a value of an internal signal and propagate this modification. I have a counter and in the third cycle of simulation, where cnt(internal signal) takes 3 I have forced it to 0 for two cycles. the problem I found is after these two cycles, the cnt takes 5 and not 1

 add_force cnt_o 0 -after 400us [two cycles] .

do you have a solution how I can fix this problem? note: it is for fault attack simulation

always_ff @(posedge clk or negedge rst_n) begin                               
    if (!rst_n) begin                  
      cnt_q <= 0;                 
    end else  begin       
      cnt_q = cnt_q + 1;         
    end
end           
assign cnt_o = cnt_q

test_bench :

logic [32 : 0] cnt;
logic clk;
logic rst_n;

counter test (.clk, .rst_n, .cnt_o(cnt) )

initial begin 
clk = 0;
rst_n = 1;
end
always begin 
clk = ~clk ;
end

toolic · Answer 1 · 2021-03-30T23:59:50.960

You should force the cnt_q signal instead of cnt_o because cnt_q retains it previous value.

Instead of using Vivado-specific commands, use force/release in the testbench. Here is a complete, working example:

module counter (input clk, rst_n, output [32 : 0] cnt_o);
logic [32 : 0] cnt_q;

always_ff @(posedge clk or negedge rst_n) begin                               
    if (!rst_n) begin                  
      cnt_q <= 0;                 
    end else begin       
      cnt_q <= cnt_q + 1;         
    end
end           
assign cnt_o = cnt_q ;
endmodule


module tb;
logic [32 : 0] cnt;
logic clk;
logic rst_n;

counter test (.clk, .rst_n, .cnt_o(cnt));

initial begin 
    clk = 0;
    rst_n = 0;
    #22 rst_n = 1;
    wait (test.cnt_q == 3);
    force test.cnt_q = 0;
    repeat (2) @(posedge clk);
    release test.cnt_q;
end

always begin 
    #5 clk = ~clk;
end
endmodule

Change value of internal signals while running simulation

1 Answers1