How to transfer part of a Xilinx HLS stream to another function?

Question

I have two variables:

void func1(hls::stream<ap_axiu<8,1,1,1>> &a);
void func2(hls::stream<ap_uint<8>> &b);

Where ap_axiu is defined as:

template<int D,int U,int TI,int TD>
  struct ap_axiu{
    ap_uint<D>       data;
    ap_uint<(D+7)/8> keep;
    ap_uint<(D+7)/8> strb;
    ap_uint<U>       user;
    ap_uint<1>       last;
    ap_uint<TI>      id;
    ap_uint<TD>      dest;
  };

I would like to call func2 inside func1, using the data of parameter a of func1 (see defenition of ap_axiu). So func would look something like this:

void func1(hls::stream<ap_axiu<8,1,1,1>> &a) {
   func2(???);
}

where ??? should be the ap_uint<D> data part of variable hls::stream<ap_axiu<8,1,1,1>> a, surrounded by hls::stream< >.

How can I do this in C++? I don't have much experience with templates and I also cannot find it on Google.

Have you read the docs for the library you're using? https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_stream_library.html — John Zwinck, Mar 29 '21 at 10:32

score 0 · Answer 1 · answered Mar 29 '21 at 11:01

0

Try this:

void func1(hls::stream<ap_axiu<8,1,1,1>> a)
{
    ap_axiu<8,1,1,1> input = a.read();
    hls::stream<ap_uint<8>> intermediate;
    intermediate.write(input.data);
    func2(intermediate);
}

The idea is to read the entire struct from a and push the one field you care about into intermediate so you can call func2.

This assumes you only want to transfer a single element from func1 to func2. A stream may contain many elements, in which case you may need to add a loop to read and write several values.

answered Mar 29 '21 at 11:01

John Zwinck

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I forgot to mention a and b can either be read or written to. I added reference signs to the a and b variables in the original post. Storing it in an intermediate variable would not work, because I need to transfer a lot of data and there are not enough resources available to store them locally. – Roy Meijer Mar 29 '21 at 11:19
1

Reference signs won't make any difference: the solution above is the **only possible way ** to go. Afterall, you're synthesizing a FIFO (hls::stream class), and by definition a FIFO has one producer side and one consumer side. In practice, you cannot use the same one to read and write to and from you IP: you need one more argument, so that one stream is only for reading and the other only for writing. If you really need to stay short on ports (or resources) use a BRAM or an AXI interface instead. – Stefano Ribes Mar 29 '21 at 12:07

How to transfer part of a Xilinx HLS stream to another function?

1 Answers1