8bit ALU line 46: Can not simplify operator DIV

Question

Hello guys I just wanted to ask how to debug this one in line 46 in says "Can not simplify operator DIV." in Verilog Module (Xilinx). Thank you in advance for the tip and help :))

Here's the code of my 8bit ALU

module alu_8fctn (a, b, opcode, rslt, rslt_mul);
input [3:0] a, b;
input [2:0] opcode;
output [3:0] rslt;
output [7:0] rslt_mul;
wire [3:0] a, b; //inputs are wire
wire [2:0] opcode;
reg [3:0] rslt; //outputs are reg
reg [7:0] rslt_mul;
//define operation codes
parameter add_op = 3'b000,
            sub_op = 3'b001,
            mul_op = 3'b010,
            div_op = 3'b011,
            and_op = 3'b100,
            or_op = 3'b101,
            xor_op = 3'b110,
            xnor_op = 3'b111;
//perform the operations
always @(a or b or opcode)
begin
case (opcode)
            add_op : rslt = a + b;
            sub_op : rslt = a - b;
            mul_op : rslt_mul = a * b;
            div_op : rslt = a / b;
            and_op : rslt = a & b;
            or_op : rslt = a | b;
            xor_op : rslt = a ^ b;
            xnor_op: rslt = a ^~ b;
            default: rslt = 8'b0000_0000;
endcase
end
endmodule

Answer 1

Your Xilinx appears to have trouble with a / b. Synthesizers can have a hard time optimizing with variable divisors; especially if they can be zero.

Xilinx should have some predefined modules for division (if not you can always make your own)

wire [3:0] rslt_div;
<XilinxPrividedDividerModuleName> div ( rslt_div, a, b);
always @*
  ...
  div_op : rslt = a / b;
  ...

---

Other issue: rslt and rslt_mul are inferred latches because they are not assign in all conditions. In mul_op and rslt_mul is only assigned in mul_op and that is the only condition rslt is not assigned.

Refer to What is inferred latch and how it is created when it is missing else statement in if condition. Can anybody explain briefly?

Simple solution is give the rslt and rslt_mul an initial/default value before the case statement.

always @*
begin
  rslt = 4'h0;
  rslt_mul = 8'h00;
  case (opcode)
    // ... you other code
  endcase
end

---

Also note that always @(a or b or opcode) is the Verilog-1995 way of writing a sensitivity list. Since Verilog-2001 the preferred way is always @* (or the synonymous always @(*)). SystemVerilog goes a step further with always_comb where a good tool should flag an error if a latch is inferred.

You may also want to consider ANSI style module headers (also available since Verilog-2001) which is less verbose and less prone to typos then the Verilog-1995 module header style.

module alu_8fctn (
  input [3:0] a, b,
  input [2:0] opcode,
  output reg [3:0] rslt,
  output reg [7:0] rslt_mul );

  //define operation codes
  parameter add_op = 3'b000,
  ...