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I am trying to code a 5-bit Mealy odd parity checker. I got some of the code written (the reset, the next state logic, and the output logic) except the part where the checking happens for the 5-bit output. How can I check a 5-bit variable if the number of 1'b1 in it is odd?

module parity(clk, rst, w,z);

input clk, rst, w; 
reg [1:0] present, next;

output reg z;

parameter s0 = 4'b0000, s1 = 4'b0001, s2 = 4'b0010, s3 = 4'b0011, s4 = 4'b0100, s5 = 4'b0101, s6 = 4'b0110, s7 = 4'b0111, s8 = 4'b1000, s9 = 4'b1001, s10 = 4'b1010;

//Reset
always @(posedge clk, posedge rst)
    
    begin 
        if(rst) 
            present <= s0;
        else 
            present <= next;
    end    


//Next State logic
always @(present, w) 
    begin 
        case(present) 
            s0: if(~w) next = s1; else next = s2;
            s1: if(~w) next = s3; else next = s4;
            s2: if(~w) next = s4; else next = s3;
            s3: if(~w) next = s5; else next = s6;
            s4: if(~w) next = s6; else next = s5;
            s5: if(~w) next = s7; else next = s8;
            s6: if(~w) next = s8; else next = s7;
            s7: if(~w) next = s9; else next = s10;
            s8: if(~w) next = s10; else next = s9;
            s9: if(~w) next = s0; else next = s0;
            s10: if(~w) next = s0; else next = s0;
            default: next = s0;     
        endcase
    end


always @(w, present)
    begin
        if (present == s10 && w == 1)
            z = 1'b1; 
        else 
            z = 1'b0;
    end


endmodule
mkrieger1
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Jordan
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1 Answers1

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If you had a 5-bit variable, like

reg [4:0] data;

you would get its odd parity by using the unary ^ (XOR reduction) operator:

odd = ^data
mkrieger1
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  • this code is the code for the MEALY part of the design. how do we add a 5-bit variable to this mealy code to check the 5-bit variable for the odd numbers of (1) – Jordan Mar 04 '21 at 16:25