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If the first cycle of each instruction is not the same (ie not all instructions have the same fetch cycle), then how does the processor know what the control signals should be for the first cycle?

I understand that usually the fetch cycle is the same for all instructions, but I am asking about the case/possibility when it is not.

OmjjICmA
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  • What kind of CPU are you talking about? A classic RISC like MIPS where instructions are fixed width? https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Instruction_decode. If not, e.g. instructions that can be either 16 or 32-bit (like RVC: https://en.wikipedia.org/wiki/RISC-V#Compressed_subset or ARM Thumb2) then either some fetches need a 2nd cycle, or you have a prefetch buffer that you decode out of, and it's not quite as simple as using bits of the instruction word directly as internal control signals (the way classic MIPS can/does). – Peter Cordes Feb 24 '21 at 05:46
  • I suppose my question was "What would the architecture of the CPU need to look like to allow the first cycle of some instructions to have different control signals?". So in this case, is the answer that it would not be possible in a classic MIPS/RISC CPU, but using fetches that have more than one cycle/ using a prefetch buffer could make it possible? – OmjjICmA Feb 24 '21 at 16:49
  • Not so much "would make it possible", but would make it *necessary* to put a thin layer of decoding between instruction-word bits and internal control signals. That layer of decoding doesn't have to take a whole cycle, just a couple gate-delays of latency for muxes / table lookup (a few input signals generate a larger set of output signals, which are used as internal control signals.) If instructions aren't fixed-width, the different lengths probably have different-enough formats that you need some real decoding before you have the right signals for register-fetch and so on. – Peter Cordes Feb 25 '21 at 01:04
  • Thanks, that's very interesting! Sorry if the question was a bit naive, I've only come across MIPS architecture. Looks like I have some reading to do. – OmjjICmA Feb 25 '21 at 02:39
  • [Modern Microprocessors A 90-Minute Guide!](http://www.lighterra.com/papers/modernmicroprocessors/) is probably a good starting point for your reading, then. :P Maybe also some stuff about modern x86 ISAs like https://www.realworldtech.com/sandy-bridge/, and less modern less complicated stuff like https://www.realworldtech.com/merom/ (Core 2), and maybe https://www.realworldtech.com/ev8-mckinley/ (Alpha vs. Itanium) – Peter Cordes Feb 25 '21 at 03:15

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