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I understand there are 5 standard stages for an instruction in MIPS. for the following pseudo instruction

li $t1, 0      # pseudo-instruction for addi $t1, $zero, 0

Can anyone please confirm if this uses all 5 stages? I think underlying this is an addi but I don't really understand if it needs to use the MEM stage?

My thinking is that the immediate value is stored in the instruction, not in memory, so wouldn't the WB stage do the register load?

Peter Cordes
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Jason Hyland
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    What does it mean to you to "use" a pipeline stage? – harold Feb 18 '21 at 20:15
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    A pseudoinstruction does not use any pipeline stages, because it is not an instruction that the processor pipeline can execute. Your question is meaningless. – EOF Feb 18 '21 at 20:53
  • Sorry, wasn't very clear - I meant all instructions are composed of a number of "stages" in the datapath pipeline (IF, ID, EX, MEM, WB) - I was asking if the 'addi' used the MEM stage. Appears not. – Jason Hyland Feb 18 '21 at 22:21
  • EOF - I put the underlying instruction there (addi) - please read more carefully, it might make a bit more sense. – Jason Hyland Feb 18 '21 at 22:25

1 Answers1

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This instruction will translate into an addi $t1, $0, 0 or some other such.

All stages do useful work to execute even such simple computational instructions — except the MEM stage.

Only load and store instructions require the data memory pipeline stage (MEM).  If it wasn't for them, we wouldn't have a MEM stage.  (Of course, we would also have a processor that can't do much, either.)

Erik Eidt
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