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From Intel Manual Volume 3a, Chapter 5.3.2 Maskable Hardware Interrupts, it says that Maskable hardware interrupts that can be delivered through INTR pin include all IA-32 architecture defined interrupt vectors from 0 through 255.

My understanding is that the first 32 vector number are reserved by Intel and first 16 are mostly execptions generated from CPUs. On the other hand, INTR pin is supposed to be used by external devices (either asserted by old 8259 PIC directly or asserted by local APIC). Why does Intel allow [0,31] vector number to be delivered through INTR? When a cpu generated exception happens, does it actually assert on the INTR?

Oliver Young
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  • Related: https://stackoverflow.com/questions/42208827/how-can-the-timer-interrupt-be-0x08-if-the-first-32-interrupts-are-reserved-for – Ross Ridge Jan 16 '21 at 21:56
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    Interrupts are numbered from 0 and you're talking about the first 32 being special. That would be [0, 32) or [0, 31]. – Peter Cordes Jan 16 '21 at 23:24
  • @PeterCordes Yeah edited the questions to fix this. – Oliver Young Jan 16 '21 at 23:48
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    As described in the answer linked by @Ross, even though these interrupts are reserved, they are used by old software (including current BIOSes). The x86 family values compatibility over nearly everything else, so it still supports them. Note that the APIC won’t post or deliver interrupt vectors less than 16, so those can only be delivered through the legacy PIC. – prl Jan 17 '21 at 00:15
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    CPU exceptions are recognized and delivered differently from interrupts, though they use the same vector table. – prl Jan 17 '21 at 00:17
  • @prl Thank you for the clarification. I didn't see Intel manual mentions how exceptions (or INT instruction) was delivered. I guess since it's completely cpu internal specifics, as programmers we simply don't care as long as they use the same IDT as external interrupts delivered via APIC or PIC? – Oliver Young Jan 17 '21 at 04:31
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    It may help you know that the OS moves all HW interrupts above the first 32 interrupts. When these first interrupts were also used for HW interrupts, the CPU had fewer exceptions and there was no conflict. The then Protected mode was invented and the OS had (and has) to move the HW interrupts so they don't overlap with exceptions. This design is mostly historical but allow for a single data structure to handle interrupts and exceptions. – Margaret Bloom Jan 17 '21 at 11:26

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