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I want to set interrupt priorities for processor internal exceptions. The cortex_m crate provides easy access to NVIC control registers. Specifically, there is a method that let me set priority for each interrupt.

let mut p = cortex_m::Peripherals::take().unwrap();
p.NVIC.set_priority(...);

set_priority asks me to pass an argument specifying for which interrupt I intend to modify the priority. Say I want to change the priority for PendSV. However, passing in cortex_m::peripheral::scb::Exception::PendSV will not work because it does not implement a required trait bound.

I am developing on STM32F407VGT6 board, so I also looked in the stm32f4 crate, but I did not find any enum definition that can help either.

Should I write my own enum that implements the required trait so that it can specify interrupt numbers, or is there already some existing crate that can make it work?

Zhiyao
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1 Answers1

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According to the documentation of InterruptNumber, implementing this Trait is responsibility of the PAC (peripheral access crate) provider. Looking at the stm32f4 crate, its latest release (0.12.1 as of time of writing) is still dependant on cortex-m >=0.5.8, <0.7, meaning the developers likely haven't upgraded to the new API yet.

The old API makes use of the bare_metal::Nr trait, which a few PACs stil rely on.

I found an example in the cortex-m-quickstart guide that makes use of the old NVIC API.

I recommend you go by the dependency requirements of your PAC and downgrade to cortex-m >=0.5.8, <0.7 and keep an eye out for updates to stm32f4.

ChiefGokhlayeh
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    I don't see definitions for processor generated interrupts in `stm32f4`. It currently only defines external interrupts. Is that correct? – Zhiyao Jan 14 '21 at 12:29
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    Yes you are correct, I missed that. PendSV is an exception, and those are generic across all cortex-m devices. The ARM Cortex-M User Guide also states, that those exceptions, which have configurable priorities, can be controlled through the NVIC. It could simply be an oversight in the current API design. You could try to implement the Nr trait yourself. – ChiefGokhlayeh Jan 14 '21 at 13:10
  • You might also find this discussion of interest https://github.com/rust-embedded/cortex-m-rt/issues/44. While quite old, it states that exceptions are to be configured through the SCB API directly. – ChiefGokhlayeh Jan 14 '21 at 13:17