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I'm relatively new to VHDL and hardware programming and I have a question regarding the port maps and signals.

I wanted to read and write to one particular signal in my current project but my lecturer told me I shouldn't use 'inout' but when I asked why he didn't elaborate. Could someone tell me why I shouldn't use it instead of a define 'in' or 'out' signal?

I'm sorry if this is a stupid question or it has been asked previously.

Thank you!

George
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This is specific to VHDL. When you define port with a mode you are giving that port certain architectural properties. Data flows in to an entity from a port with mode IN. Data only flow out of an entity for port with mode OUT. Thus you can not read an OUT port inside of your entity. Assume you have a foo: out std_logic; You CANNOT write an expression that says fi <= foo; This should cause an error when you compile.

I am not making a case to make foo: inout std_logic; but that would be one rational for maybe doing it. The inout allows for assignment and reading.

If I didn't need to have the port as an input on the entity, I would have assigned it as a an OUT personally. I would have used an internal signal for assignment and reading, and driven the out port from the signal.

Rich Maes
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    FYI: VHDL 2008 allows reading of output ports – maximus Dec 08 '20 at 20:24
  • A mode out port in -2008 matches the behavior of mode buffer which can be used with implementations relying on earlier revisions of the standard. –  Dec 08 '20 at 21:07