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Good day. I am trying to make an ALU that adds, subtracts, multiplies (3X2 bits), and makes logical operations. For that, I chose to use libraries, and the sentence "with... select...". The problem is in the multiplier, that one is well, I used an adder and I fixed it according to what I need, that part compiles, but when I put it in the sentence "with...select..." it throws a problem, and the error it throws is:

Blockquote "1039 VHDL Interface Declaration error in alu.vhd(69): interface object "r" of mode out cannot be read. Change object mode to buffer"

Am I "invoking" the multiplier wrong? what can I do? Thank you very much. The code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity alu is 
port(
        s: in std_logic_vector (2 downto 0);
        a: in std_logic_vector (3 downto 0);
        b: in std_logic_vector (3 downto 0);
        ci: in std_logic;
        co: out std_logic;
        r: out std_logic_vector (4 downto 0);
        f: out std_logic_vector (4 downto 0)
        );
end alu;

architecture comportamiento of alu is

component sumador
    port(
        a: in std_logic;
        b: in std_logic;
        ci: in std_logic;
        co: out std_logic;
        e: out std_logic
        );
    end component;

    signal x: std_logic_vector (4 downto 0);
    signal y: std_logic_vector (1 downto 0);

    begin
    r(0)<= a(0) and b(0);
    x(0)<= a(1) and b(0);
    x(1)<= a(0) and b(1);
    x(2)<= a(2) and b(0);
    x(3)<= a(1) and b(1);
    x(4)<= a(2) and b(1);

    u0: sumador port map (
    a=> x(1),
    b=> x(0),
    ci=> '0',
    co=> y(0),
    e=> r(1)
    );

    u1: sumador port map (
    a=> x(3),
    b=> x(2),
    ci=> y(0),
    co=> y(1),
    e=> r(2)
    );   

    u2: sumador port map (
    a=> x(4),
    b=> '0',
    ci=> y(1),
    co=> r(4),
    e=> r(3)
    );
    
    with s select
    f<=         a+b         when "000",
            a-b         when "001",
            r       when "010",
            a or b      when "011",
            a xor b     when "100",
            a and b     when "101",
            a       when others;
            

end comportamiento;

thank you very much for your help

Pablovick
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  • Which line is line 69? – mkrieger1 Nov 14 '20 at 22:04
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    Does this answer your question? [VHDL buffer variable vs out variable](https://stackoverflow.com/questions/46026767/vhdl-buffer-variable-vs-out-variable) – mkrieger1 Nov 14 '20 at 22:07
  • There are other issues with your code. For instance the selected signal assignment to f has a target length of 5 and most selected expressions have a length of four. There's a requirement for matching elements in assignment. –  Nov 14 '20 at 23:29
  • line 69 -> r when "010" – Pablovick Nov 15 '20 at 03:18
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    The specific error is because your VHDL language version is set to VHDL2002 or earlier. Outputs can only be read in VHDL2008 and later. – Tricky Nov 15 '20 at 08:54

0 Answers0