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So I am looking at some riscv assembly code and basically trying to figure out what's wrong. However, I stumbled upon the following code:

 80001a2:   00000097            auipc   ra,0x0
 80001a6:   62e080e7            jalr    1582(ra) # 80007d0 <memset>

I think I understand the auipc, namely adding the pc to my return address, however I don't understand the jalr here. When I look it up, it says the usage is:
jalr xD, xL (offset)
I am guessing in my code the (ra) is the offset, but what is 1582 here? The source? the destination? both?

Peter Cordes
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Vvamp
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    _The RISC-V Instruction Set Manual Volume I: User-Level ISA_ has a table of pseudo-instructions, in which it says that `jalr rs` expands to `jalr x1, rs, 0` (with `x1` just being a different name for `ra`). So by extension, `jalr rs, imm` ought to expand into `jalr x1, rs, imm` – Michael Nov 05 '20 at 11:23

1 Answers1

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Presumably the disassembler assumes the normal default destination register (ra) to write the return address into, so leaves that implicit.

So 1582(ra) would be how it shows the target address calculations, like an addressing mode for a load or store, offset(reg). RISC-V jalr supports some immediate offset bits, making it possible to call any target address with a 2-instruction sequence of auipc to get 20 bits of relative offset, and jalr supplying the other 12. That's pretty clearly what's going on here. Understanding the auipc+jalr sequence used for function calls

If you want to double-check, disassemble it yourself.

(The 0x0 offset in the auipc instruction might be due to memset having ended up nearby. These look like "real" addresses so it's not an unlinked .o. I'm guessing this is a statically-linked executable? The fact that memset would be so close wasn't known until link time; too late to optimize to a jal relative branch I guess.)

Peter Cordes
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