1

My confusion is based on these 3 thoughts -

  1. Is it 2^(number of all address pin available on the cpu)?

  2. Is it the 2^(size of one specific register)?

  3. Is it a hardware circuit which understands all the addresses within a range of addresses? Then what is it?

I'm not asking about virtual address space here, I don't know what it's called , maybe it's the physical address space of all physical devices including ram. Besides even if I get a correct answer then I would like to ask, why does my cpu has 2^39 bits(512GB) of memory address space and 64KB+3 I/O memory space. This information is written on intel documentation for my system in package (intel core i3-4005U with an integrated lynx point-m PCH).

You are welcome to edit my question if I'm asking it wrong. Thank you.

Peter Cordes
  • 328,167
  • 45
  • 605
  • 847
bipul kalita
  • 25
  • 7

1 Answers1

2

The size of physical address space for a CPU is an arbitrary choice made by the designers. The width of cache tags and TLB entries have to be wide enough because caches are physically tagged (including L1d in most CPUs, including all Intel), and other internal things that deal with physical addresses. (Like the store buffer, for matching load addresses against outstanding stores. And also for matching stores against in-flight code addresses.)

All Haswell-client CPUs share the same core microarchitecture, so even though a laptop chip doesn't need that much, some single-socket non-Xeon desktops might. (I think this is true; saving a small amount of space and/or power by changing cache tag widths by 1 or 2 bits might plausible but IDK if Intel does that; I think they really only want to validate a design once.)

Remember that device memory (including PCIe card such as VGA or a Xeon Phi compute card) will normally be mapped into physical address space so the CPU can access it with loads/stores (after pointing virtual pages at those regions of physical address space). PCIe uses fixed width links and sends addresses as part of message "packets"; no extra pins are required for more addresses.

The DDR3 DRAM controllers have a number of address lines on each channel to send row/column addresses; it might be possible to leave one pin unused. It's very similar to other DDR versions; Wikipedia has diagram of some of the signals in the DDR4 article: https://en.wikipedia.org/wiki/DDR4_SDRAM#Command_encoding

Peter Cordes
  • 328,167
  • 45
  • 605
  • 847
  • Thank you for your effort. You said "The size of physical address space for a CPU is an arbitrary choice made by the designers", let's say they decided to make it 39 bit width. Then what hardware circuitry will be changed for that. I'm really confused still. – bipul kalita Nov 05 '20 at 11:48
  • 1
    @bipulkalita: Like I said, cache tags in L1d/L1i, L2, and L3 caches, iTLB and dTLB, and 2nd-level TLB, and store buffer entries and their comparators, self-modifying code detections, and probably some actual I/O related stuff in the "system agent" hop on the ring bus. http://www.realworldtech.com/haswell-cpu/ doesn't make a big deal out of physical address width, but have a look over the block diagram and keep in mind anything that deals with physical addresses. – Peter Cordes Nov 05 '20 at 11:53
  • that's a really satisfying answer but I need a full lists of "other things". – bipul kalita Nov 05 '20 at 11:56
  • @bipulkalita: Updated my previous comment. *Why* do you need this full list? What are you going to do with it? Surely it's not going to affect a program you'd write, and if you were designing your own CPU you'd notice everywhere you have a physical address. – Peter Cordes Nov 05 '20 at 11:58
  • sorry, I edited my question that's why it's displaying below. I need to learn these things, I need accurate and specific information. It's really hard for me to look into a book and search on the Internet and can't find anything for me. I want to break all abstract layers of highlevel informations and so I can actually see what's hapenning below. – bipul kalita Nov 05 '20 at 12:03
  • 1
    @bipulkalita: I don't think it's necessary to track down every single use of physical addresses inside a Haswell CPU. The major factors (and some other minor ones that occurred to me) are the ones I listed in my first comment, especially cache tag width. The key point is that it's *not* tied to register width or external CPU pins, or even to how much DRAM it can support. – Peter Cordes Nov 05 '20 at 12:10
  • The best book you can suggest me to learn all these low level things? It surprises me that not even in William Stallings book it's written about how the physical address is defined. I'm a graduated student from cs. But I think I did not gain much in my degree. That's why I have failed in some competitive exams. – bipul kalita Nov 05 '20 at 19:31
  • 1
    It's not really an arbitrary choice, it's determined according to the requirements of the target market segments. Another important impact that the physical address width has is on the number of wires for carrying the physical address bits all over the chip. Address multiplexing could be used if there is no impact on performance or if performance is deemed less important than cost. The number of address pins on the package is determined by the maximum amount of physical memory supported, which is a different limit and design choice. (The legacy IO space has nothing to do with these limits.) – Hadi Brais Nov 08 '20 at 22:38
  • 1
    The number of address pins on the package is determined by the maximum amount of physical memory supported per channel and the number of channels. – Hadi Brais Nov 08 '20 at 22:40
  • 1
    @HadiBrais: Of course it's not arbitrary in that sense, but it's not directly implied by any of the factors the question proposed. Making a *good* / successful product is a matter of making the correct choice for lots of "arbitrary" choices. e.g. pipeline width, cache sizes, ALU design, register width, handling of corner cases relevant to backwards compatibility... – Peter Cordes Nov 09 '20 at 01:52