Often I get the error message
WARNING: [RTGEN 206-101] Port 'xy' has no fanin or fanout and is left dangling. Please use C simulation to confirm this function argument can be read from or written to.
C simulation and synthesis passes. What is the general reason ports are sometimes left dangling? How can I debug it? And is it important to resolve them?
That warning usually comes if some ports, i.e. function arguments, are never utilized in your C/C++ code. It might happens that the compiler/Vivado HLS simply optimizes away parts of the code where the arguments/ports are never accessed or never reached.
This last condition might actually help finding spots of a buggy algorithm. For instance: an if-else statement can be resolved in only one branch always being executed, thus leaving out the arguments processed in the other branch (and therefore generating dangling ports).
In general the warning causes the generated RTL to still have the defined ports, but just having them unconnected to anything. They are usually not an issue in later generation steps, since they might be further optimized away and removed (during synthesis or optimization, before generating the bitstream).
