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I have a top file in Verilog and it uses multiple modules instantiated in it that are in different files. If I put all these files in one directory and then I use read Verilog command only on the top file. Will all the files having the modules are be read by this command in the correct order?

Muhammad Amir Altaf
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1 Answers1

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If your Verilog files are named after the modules they contain:

read_verilog top.v
hierarchy -top top -libdir .

otherwise, you will have to read in all the modules:

read_verilog *.v
hierarchy -top top
gatecat
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  • Hi @gatecat, I have few files [ahb_master.v, ahb_slave, decoder.v, multiplexor.v, ahb_top.v]. I saved them in the same directory. I made a script file[named: script.ys]. I changed its permissions using **chmod +x script.ys** On running using **./script.ys** it is saying **command not found**. The script has two lines saying: **read_verilog ahb_top.v hierarchy -top top -libdir . ** I have named my files after my modules. – SWETHA CHILVERI Mar 27 '22 at 09:06
  • I also tried using: ** yosys -o synth.v -p hierarchy -p proc -p opt -p memory -p opt -p fsm -p opt -p "show -colors 1 -viewer touch -format svg" -f verilog ahb_master.v ahb_slave.v decoder.v multiplexor.v ahb_top.v** At the end it says: **For formats different than 'ps' or 'dot' only one module must be selected** – SWETHA CHILVERI Mar 27 '22 at 09:07