what is the the hardware fifo size of STM32f103CB and how to know whether the FIFO is empty or full?

Question

As the title mentioned, I can't find relevant information in the datasheet.

I get some problem when using UART. I have two chips, the master chip transmits packages to RS485 Bus line, and the slave chip receives it then transmits the respond(UART1), at the same time, every second the timer will transmit debugging stuff to pc by TTL(UART2), they should be mutual independent, however the UART1 doesn't work when UART2 is working, and the data is still transmiting to RS485 bus from master chip, so some of the data will not received by slave chip when slave chip is using UART2, after a while whole system on slave chip get weird (the timer is still working), I guess it is the FIFO overflow. So I am asking for function or ways to know the fifo size remain.

Thanks.

STM32F103CB has not FIFO. For both direction, it has a shift register and a data register. So you write the next byte while the current one is being transmitted (and similar for reception). You might want to look into DMA transfers. — Codo, Aug 25 '20 at 06:32

Zongru Zhan · Accepted Answer · 2020-08-27T09:16:10.323

As Codo comments, this chip has not FIFO with USARTs.

after a while whole system on slave chip get weird

So your problem is not caused by the lackness of FIFO.

Besides using DMA for transfering, you could also use interrupt preemption to receive while transfer.

uart2_rcv_isr() {
  receive_from_uart2();
}

timer_isr() {
  mark_flag_for_uart1_transfer();
}

main() {
   if(flag_for_uart2) {
      reply_with_uart2();
      unflag_uart2_task();
   }

   if(flag_for_timing_task) {
      transfer_with_uart1();
      clear_timing_task_flag();
   }
}

what is the the hardware fifo size of STM32f103CB and how to know whether the FIFO is empty or full?

1 Answers1