what is the the difference between Dataflow model and RTL style coding in verilog/SystemC

Question

I have studied in my school that both the models are used in same perspective but when i went through online there are pages which define some tips to convert Dataflow models to RTL models, so can someone explain me with an example what is the difference exactly. Thanks in advance.

Answer 1

This is a data flow model

module #(parameter width = 8) array_multiplier(    
     input [width-1:0] a, b,
     output [width-1:0] y
);
   assign Y = a * b;
endmodule

This is an RTL model of a multiplier (extracted from here)

module #(parameter width = 8) array_multiplier_(    
     input clk,
     input [width-1:0] a, b,
     output [width-1:0] y
);   
reg [width-1:0] a_pipeline [0:width-2];
reg [width-1:0] b_pipeline [0:width-2];
reg [width-1:0] partials [0:width-1];
integer i;

always @(posedge clk) begin
    a_pipeline[0] <= a;
    b_pipeline[0] <= b;
    for (i = 1; i < width-1; i = i+1) begin
        a_pipeline[i] <= a_pipeline[i-1];
        b_pipeline[i] <= b_pipeline[i-1];
    end

    partials[0] <= a[0] ? b : 0;
    for (i = 1; i < width; i = i+1)
        partials[i] <= (a_pipeline[i-1][i] ? b_pipeline[i-1] << i : 0) +
                partials[i-1];
end

assign y = partials[width-1];

endmodule