What is the Hardware synthesized for << operator

Question

I have recently started working on HDL , while going through right/left shift operators what i have studied in my school was they are continous D FlipFlops that shift data bit by bit to result the output.

I assumed same will be done over while synthesizing them in hdl, but i couldn't see the same hardware in verilog synthesis , its appearing like simple concatenation operations in the RTL_LSHIFT.

Could some one explain me how actually the hardware will be inside this RTL_LSHIFT. If it is FF's then why there is no clock input to the BLock.

I know all the functionality of arithmetic and logic shift, I need the hardware synthesized in HDL.

Code:

module doubt(
    input[5:0] a,
    input [5:0] b,
    input clk,
    output reg [9:0] c,
    output reg [9:0] d
    );
    reg s1,s2;
    always @ ( posedge clk)
   begin 
   
   c <= (a<<1);
   d<= (b<<4);
    end  
endmodule

please click on the "enter image description here" for the image new to stack sorry, also sorry for the code , i dont know it ill show up like that. Thanks in advance — Nikhil Chandra, Jul 22 '20 at 06:24
`RTL_LSHIFT` is setting the correct bit order, but your FF's are "hidden" inside `RTL_REG`. — Qiu, Jul 22 '20 at 06:35

m4j0rt0m · Answer 1 · 2020-07-23T09:46:41.487

0

In hardware, a left/right shifter is a simple set of multiplexers, take a look at the barrel shifter's design. Also, it depends on the EDA synthesizer how this is inferred and possibly optimized.

edited Jul 23 '20 at 09:46

answered Jul 22 '20 at 10:02

m4j0rt0m

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1
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But how come this could be a optimized solution in terms of AREA on chip and power consumption ? why not simple D ff with clock is used ? – Nikhil Chandra Jul 23 '20 at 08:00
I updated my answer. Nevertheless, if you need a single position shift per cycle or a static (not variable) amount of shifting, the logic is optimized with some connected FFs Q/D wires and enable logic for the clock. – m4j0rt0m Jul 23 '20 at 09:50

score 0 · Answer 2 · answered Jul 27 '20 at 09:18

The real Flip-Flops reside in the RTL_REG. The RTL_LSHIFT rearranges bit order of input vectors. I'm not familiar with the tool you used to generate this schematic (maybe from Xilinx I think), so I don't know what I0/I1/I2 all about either. In addtion, if your question is limited to fixed shift position, like left shift by exactly 2 bits, we'd like to use this concatenation form out <= {in[3:0], 2'b0}; (givenout and in are both 6-bit signals) instead. This makes our code more precise, and reduces potential bugs. Sorry that due to time and the computer I'm currently working on, I have no suitable tools to draw a schematic.

score 0 · Answer 3 · answered Aug 07 '20 at 19:46

For a constant shift, wires are used. You just wire each input bit to the right output position. No other parts are needed.

In your example, a[0] is wired to the d input of c_reg[1], a[1] is wired to the d input of c_reg[2], etc.. The unassigned bits are wired to 0. Because c[7:9] are always 0, your tool has wired the outputs directly to 0, without a flip flop.

In an FPGA, the wires are themselves multiplexers programmed by the bitstream that is downloaded to the FPGA, but conceptually a fixed shift is still a wire.

In other implementation technologies and/or optimizers, I am sure c[0] will be wired to 0 as well.

If the shift is not constant you need the barrel shifter described by m4j0rt0m.

What is the Hardware synthesized for << operator

3 Answers3