-2

Since ARM32 machine instructions can be executed directly on ARM64 processors, I thought that the machine code of the ARM32 instruction add r0, r0, r1 should be the same as that of one of these two ARM64 instructions:

add w0, w0, w1
add x0, x0, x1

However, after objdump some .o file, I found that it is not the case. The machine code for them is like this:

e0800001    add r0, r0, r1
0b010000    add w0, w0, w1
8b010000    add x0, x0, x1

Then I tried to find what e0800001 means in ARM64, but I didn't find any opcode in ARM64 that begins with 0xe0. I searched the documents about opcodes of ARM64 on https://github.com/CAS-Atlantic/AArch64-Encoding

xiaokaoy
  • 1,608
  • 3
  • 15
  • 27
  • "Since ARM32 machine instructions can be executed directly on ARM64 processors," - they can't, you have to switch instruction sets before, similar to how you need to switch between Thumb (T32) and ARM (A32). – Erlkoenig Jul 17 '20 at 08:46
  • See [this](https://stackoverflow.com/a/60532434/4730685). The kernel can switch between AArch64 and AArch32 upon exception return. – Erlkoenig Jul 17 '20 at 09:06
  • refer to the actual arm documentation if you want to know about arm instructions. – old_timer Jul 17 '20 at 14:04
  • the arm documentation clearly documents aarch32 vs aarch64, how to switch modes, etc. What part of the arm documentation did you not understand? – old_timer Jul 17 '20 at 14:04
  • This is no different in concept than thumb mode vs arm mode. Two different instruction sets that you need to switch modes to use. Bits are bits so naturally there are going to be bit patterns that overlap with real instructions in the various instruction sets (incompatible instructions). This is not like the x86 where the instruction set was recycled from 16 to 32 to 64 bit. This is a whole new instruction set from scratch. – old_timer Jul 17 '20 at 15:29
  • @old_timer: I would see one major difference though: you can compile/assemble/llink arm32 and thumb code in the same program, with the same set of compiler.assembler/linker. With Aarch64/Aarch32, you have to build the Aarch64 binary with one set of compiler/assembler/linker , and the Aarch32 binary with another. – Frant Jul 18 '20 at 05:11
  • 1
    The difference to ARM (A32) vs Thumb (T32) is that the switch to/from thumb can be "directly" done via the `BX` instruction, even within the same application. It's not unusual to switch between A32/T32 depending on performance needs. The switch between AArch32/AArch64 has to be done via the kernel level, and e.g. Linux doesn't support apps that use both instruction sets, so each app is either 32 or 64 bit. Therefore, the switch isn't that easy/direct. – Erlkoenig Jul 18 '20 at 09:41
  • @Frant sure due to the nature of how history played out and that thumb originally was a one to one subset of a selection of high level arm instructions one toolchain for those instruction sets is how most folks implemented it. With a new instruction set came a new backend and that made sense too (for popular toolchains like gcc). At the same time x86 has several/many incompatible assembly languages (att vs intel is only a tiny fraction of this) that became incompatible as the instruction set changed. This was just a high level view of trying to demonstrate that the bit patterns dont overlap – old_timer Jul 18 '20 at 16:42
  • @Frant how about bits are bits, just because some mips instruction set bit patterns overlap with real (defined) arm instructions doesnt mean that they have to be compatible or share the same instruction set bit pattern space. In the same way that aarch32 and aarch64 instruction sets are completely independent (just like arm and mips are completely independent) instruction sets and do not share the same bit pattern space. You are in one mode or the other. – old_timer Jul 18 '20 at 16:48

1 Answers1

3

You're making a lot of baseless assumptions.

Quoting the ARMv8 Architecture Reference Manual:

A1.3.2  The Armv8 instruction sets

In Armv8 the possible instruction sets depend on the Execution state:

AArch64   AArch64 state supports only a single instruction set, called A64. This is
          a fixed-length instruction set that uses 32-bit instruction encodings.

          For information on the A64 instruction set, see Chapter C3 A64 Instruction Set Overview.

AArch32   AArch32 state supports the following instruction sets:

          A32     This is a fixed-length instruction set that uses 32-bit
                  instruction encodings
          T32     This is a variable-length instruction set that uses both
                  16-bit and 32-bit instruction encodings.

TL;DR: You have 3 instruction sets that have nothing to do with each other.

Furthermore, your claim that...

ARM32 machine instructions can be executed directly on ARM64 processors

...is not at all true for all ARMv8 CPUs.
If we look at the register description for ID_AA64PFR0_EL1 (page D13-3255):

EL3, bits [15:12]
          EL3 Exception level handling. Defined values are:

          0b0000      EL3 is not implemented.
          0b0001      EL3 can be executed in AArch64 state only.
          0b0010      EL3 can be executed in either AArch64 or AArch32 state.

          All other values are reserved.

EL2, bits [11:8]
          EL2 Exception level handling. Defined values are:

          0b0000      EL2 is not implemented.
          0b0001      EL2 can be executed in AArch64 state only.
          0b0010      EL2 can be executed in either AArch64 or AArch32 state.

          All other values are reserved.

EL1, bits [7:4]
          EL1 Exception level handling. Defined values are:

          0b0001      EL1 can be executed in AArch64 state only.
          0b0010      EL1 can be executed in either AArch64 or AArch32 state.

          All other values are reserved.

EL0, bits [3:0]
          EL0 Exception level handling. Defined values are:

          0b0001      EL0 can be executed in AArch64 state only.
          0b0010      EL0 can be executed in either AArch64 or AArch32 state.

          All other values are reserved.

It is thus possible for an ARMv8 CPU to not support AArch32 at any exception level. And an example for such a CPU is Apple's A11, featured in the iPhone 8 and X.

Siguza
  • 21,155
  • 6
  • 52
  • 89