How can compute Bandwidth for Caches SRAM with benchmarks simulation?

Asked Jun 12 '20 at 00:13

Active Jun 12 '20 at 00:13

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please , which equation can be used to find the total bandwidth for cache L2 SRAM with Benchmark running by gem5 simulation , we have BW(read+write ) for SRAM from Destiny tools , but how can compute the BW with running benchmarks ?

asked Jun 12 '20 at 00:13

Furat Al-Obaidy

How do you define the cache bandwidth? Max bandwidth for an all-hit access (this is likely a SimObject input parameter? Or the bandwidth for a given experiment? If for a given experiment, how does it differ from DRAM bandwidth? Have you looked through the stats to see if anything of interest? – Ciro Santilli Jun 12 '20 at 06:45

How can compute Bandwidth for Caches SRAM with benchmarks simulation?

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