Xilinx System generator can be used for a cosimulation between the original MATLAB reference model and the actual HW board. Can we follow a similar procedure for a cosimulation between the original C++ reference model (before datatype and algorithm optimization for HDL) and the actual HW board in VIVADO HLS?
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Yes, we can! If you already have a C++ reference model you can compare its results with the host and device side code accelerated on FPGA. I use host/device terminology as in OpenCL which is what Vitis currently uses for C++ FPGA kernels. Typically all buffer handling across PCIe to/from FPGA is done by the host side code while data is operated upon by the device side code. Vitis and SDAccel (earlier version) flows have software emulation of code for FPGA as well as hardware emulation which is actually a co-simulation by xsim of the host and device portions of the code. Finally, you can run FPGA compiled into a bitstream on the actual hardware board (e.g. AWS F1 instance). You have your C++ original model to compare to 2 emulations and actual execution on FPGA.
My Name
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I am sorry, but what are the two emulations you mentioned here? – Cindy Jun 26 '20 at 14:46
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I have used OpenCL for GPU programming a lot. Can somebody clarify how OpenCL is related to FPGA? – Cindy Jun 26 '20 at 23:05
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Chapter 13 of this user guide will address 2 emulation and 1 real target for OpenCL and HLS C/C++ kernels on Xilinx FPGAs xilinx.com/support/documentation/sw_manuals/xilinx2019_2/… Intel OpenCL also has CPU emulation addressed in this guide: intel.com/content/www/us/en/programmable/documentation/… OpenCL is a de-facto high-level execution model if not the de-facto language of running parallel workloads on FPGAs. Some may suggest that for Xilinx it is HLS C/C++, though current Vitis uses OpenCL host API. – My Name Jun 27 '20 at 20:23