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actually this my university project and I need how to write a Verilog code if anyone can help? I need the Verilog code.. thanks

project statement:

Aim of this project is to add the “done” signal and remove the “push button” for incrementing the program counter. The program counter will be automatically incremented till the end of program and it will stop when the done signal becomes high. check comments for more details.

the Verilog code for program counter is as follows:

module counter_pushbutton(clk, rst, push_button, pc);
input clk, rst, push_button;
output [15:0] pc;

reg [15:0] pc;
reg [15:0] pc_r;


reg push_button_r, pc_en;

always @  (posedge clk or posedge rst)

      begin
          if ( rst )
              push_button_r <= 1'b0;
          else
              push_button_r <= push_button;
      end

always@*

  pc_en <= push_button & ~ push_button;

always@    (posedge pc_en or posedge rst)

  begin
      if (rst)
          pc_r <= 1'b0;
      else 
          pc_r <= pc+1;
  end

assign pc = pc_r;

endmodule

Click to view image

cryptor
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  • here is details.... so we a have program named program counter which gets incremented by the push of a button for which we have input push_button, reset, clk.... now if we press reset the program counter goes to zero and when we push push_button it get incremented... now we have to write a Verilog code to add the done logic which is given above and remove the push_button… so the program counter will automatically be incremented till the end of the program and will stop when the done signal is high? – cryptor Jun 08 '20 at 17:13
  • I think this line is wrong: `pc_en <= push_button & ~ push_button;` should be `pc_en <= push_button & ~ push_button_r;` – mcleod_ideafix Jun 08 '20 at 23:38
  • Show us what you tried so far. a) if pc is not to be incremented because of the push button, which signal will make it? How can you avoid pc from incrementing if `Done` is high? It's actually very easy! – mcleod_ideafix Jun 08 '20 at 23:41
  • the pc should automatically increments... and done is any number for example done is number 8 so whenever the memory reads a number 8 it have to stop the program counter... – cryptor Jun 09 '20 at 04:30

1 Answers1

0

Here is a code where the PC will stop whenever it reaches "pc_stop" (input port), there is an equal comparison between pc_r and pc_stop, pc_r will only increment if "done" is "0":

module counter_pc (/*AUTOARG*/
   // Outputs
   pc, done,
   // Inputs
   clk, rst, pc_stop
   );

  input           clk;
  input           rst;
  input   [15:0]  pc_stop;
  output  [15:0]  pc;
  output          done;

  reg [15:0] pc_r;

  assign done = pc_r == pc_stop;

  always @ (posedge clk or posedge rst) begin
    if(rst)
      pc_r <= 16'd0;
    else begin
      if(~done)
        pc_r <= pc_r + 16'd1;
    end
  end

  assign pc = pc_r;

endmodule // counter_pc

You can test it with:

module counter_pc_tb ();

  //..local parameters
  localparam PC_STOP = 511;

  //..regs and wires
  reg           clk;
  reg           rst;
  wire  [15:0]  pc;
  wire          done;
  wire          reached_max_pc;
  wire  [15:0]  pc_stop = PC_STOP;

  //..initialization
  initial begin
    clk = 0;
    rst = 1;
    $dumpfile("counter_pc.vcd");
    $dumpvars();
    $display("[+] Starting simulation");
    $monitor("  [+] PC: %d", pc);
  end

  //..clk signal
  always
    #1 clk = ~clk;

  //..rst signal
  always
    #10 rst = 0;

  //..pc timeout
  assign reached_max_pc = &pc;

  //..finish simulation
  wire finished_sim = reached_max_pc | done;

  //..simulation
  always @ (posedge clk) begin
    if(finished_sim) begin
      if(done)
        $display("[!] Reached PC: %d ==> Stop!", pc_stop);
      else
        $display("[!] Reached maximum PC ==> Timeout!");
      $display("[+] Ending simulation");
      $finish;
    end
  end

  //..dut
  counter_pc
    dut (
      .clk          (clk),
      .rst          (rst),
      .pc_stop      (pc_stop),
      .pc           (pc),
      .done         (done)
    );

endmodule // counter_pc_tb
m4j0rt0m
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