actually this my university project and I need how to write a Verilog code if anyone can help? I need the Verilog code.. thanks
project statement:
Aim of this project is to add the “done” signal and remove the “push button” for incrementing the program counter. The program counter will be automatically incremented till the end of program and it will stop when the done signal becomes high. check comments for more details.
the Verilog code for program counter is as follows:
module counter_pushbutton(clk, rst, push_button, pc);
input clk, rst, push_button;
output [15:0] pc;
reg [15:0] pc;
reg [15:0] pc_r;
reg push_button_r, pc_en;
always @ (posedge clk or posedge rst)
begin
if ( rst )
push_button_r <= 1'b0;
else
push_button_r <= push_button;
end
always@*
pc_en <= push_button & ~ push_button;
always@ (posedge pc_en or posedge rst)
begin
if (rst)
pc_r <= 1'b0;
else
pc_r <= pc+1;
end
assign pc = pc_r;
endmodule