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I have a board which acts as the I2C master. There is only one master. It is connected to two slaves. One slave supports clock stretching while the other does not. Between a read or write transaction, the line is pulled low. Is it possible that the slave will not pull the line low?

omkar kale
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    We need more context. Please show us some wave forms, you can draw them with any graphic program, if necessary. – the busybee Jun 05 '20 at 09:38

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Frome Wikipedia, Physical layer paragraph :

While SCL is low, the transmitter (initially the master) sets SDA to the desired value and (after a small delay to let the value propagate) lets SCL float high. The master then waits for SCL to actually go high; this will be delayed by the finite rise time of the SCL signal (the RC time constant of the pull-up resistor and the parasitic capacitance of the bus) and may be additionally delayed by a slave's clock stretching. Once SCL is high, the master waits a minimum time (4 μs for standard-speed I²C) to ensure that the receiver has seen the bit, then pulls it low again. This completes transmission of one bit.

So yes the master can pull the SCL line low. It's a normal end of transmission.

Welgriv
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