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The normal practice is to wrap the CAS instruction in a while loop on platforms that support CAS instructions. But platforms such as SPARC don't have atomic CAS instructions.

Peter Cordes
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yeshengm
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  • Platforms without atomic CAS provide some other way to do atomic operations, typically LL/SC https://en.wikipedia.org/wiki/Load-link/store-conditional which can be used to implement an atomic exchange or CAS – Peter Cordes Jun 01 '20 at 07:25
  • A comment on [How are mutexes implemented?](https://stackoverflow.com/posts/comments/1427368) points this out, but none of the answers do. Of course CAS isn't the minimal building block; any way of doing Test-and-Set is fine. – Peter Cordes Jun 01 '20 at 07:32
  • Related: https://stackoverflow.com/a/56383038/412080 – Maxim Egorushkin Jun 01 '20 at 09:07

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SPARC v8 (32-bit) and earlier lack CAS, but v9 (64-bit) does have CAS.

For a spin-lock v7 and v8 provide LDSTUB which is an atomic-read-modify-write of an unsigned byte, which writes 0xFF. That does the lock phase of a spin-lock. An ordinary write of 0 (or anything not 0xFF) will unlock, when using TSO -- for PSO you need an STBAR before the write. [There is also the SWAP atomic-read-modify-write, which can be used in the same way.]

To implement CAS (and Fetch-Op) operations on v7/v8 you need an auxiliary spin-lock.

More generally:

  • (and as noted in comments) for "modern" devices, if CAS is not supported then some form of "LL/SC" probably is...

    ...and a CAS operation can be synthesized using LL/SC. [FWIW: LL/SC is more general than CAS and avoids the dreaded ABA that straight CAS is prone to :-(]

  • but otherwise, once you have a spin-lock you can simulate most things...

    ...but if the thread holding a spin-lock goes to sleep, everybody gets to wait :-(

Machines (now historic) which provide neither LL/SC nor hardware support for a spin-lock may well have sequentially-consistent memory. In which case you can implement a spin-lock using Peterson's Algorithm, or Burns', or others'), in software.

Chris Hall
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    Essentially all modern ISAs that lack a hardware CAS provide [LL/SC](https://en.wikipedia.org/wiki/Load-link/store-conditional). Both are fully general building blocks for lockless algorithms, not just spinlocks. stdatomic `compare_exchange_weak` (instead of strong) exists specifically because of LL/SC machines, because it can be implemented without a retry loop, just a handful of instructions. Anyway, interesting that SPARC v7 specifically has a test-and-set instruction; I hadn't known of an example of an ISA that actually provided just that but not fully general atomic RMWs. – Peter Cordes Jun 01 '20 at 12:34