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I'm new in VHDL and have simple errors.

Basically I have 4 binary inputs and 3 binary outputs. The conditions are simple, if in all 4 inputs I have only one '1', output l3 receives '1' and the others '0', if I have two '1', output l2 receives '1' and the too much '0' and if I have more than two '1' the output l1 receives '1' and the others '0'.

Basically J1, J2, J3 and J4 are inputs. L1, L2 and L3 are outputs. You can verify the truth table.

I'm tryind solve this with this code in EDA Playground (https://www.edaplayground.com/)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SistemaVotacion IS
PORT (j1, j2, j3, j4: IN std_logic;
      l1, l2, l3: OUT std_logic);
END SistemaVotacion;

ARCHITECTURE SistemaArchitecture OF SistemaVotacion IS
BEGIN
    l1 <= '1' WHEN (j1 = '0' and j2 = '1' and j3 = '1' and j4 = '1')
    ELSE '1' WHEN (j1 = '1' and j2 = '0' and j3 = '1' and j4 = '1')
    ELSE '1' WHEN (j1 = '1' and j2 = '1' and j3 = '0' and j4 = '1')
    ELSE '1' WHEN (j1 = '1' and j2 = '1' and j3 = '1' and j4 = '0')
    ELSE '1' WHEN (j1 = '1' and j2 = '1' and j3 = '1' and j4 = '1')
    ELSE '0';
    l2 <= '1' WHEN (j1 = '0' and j2 = '0' and j3 = '1' and j4 = '1')
    ELSE '1' WHEN (j1 = '0' and j2 = '1' and j3 = '0' and j4 = '1')
    ELSE '1' WHEN (j1 = '0' and j2 = '1' and j3 = '1' and j4 = '0')
    ELSE '1' WHEN (j1 = '1' and j2 = '0' and j3 = '0' and j4 = '1')
    ELSE '1' WHEN (j1 = '1' and j2 = '0' and j3 = '1' and j4 = '0')
    ELSE '1' WHEN (j1 = '1' and j2 = '1' and j3 = '0' and j4 = '0')
    ELSE '0';
    l3 => '1' WHEN (j1 = '0' and j2 = '0' and j3 = '0' and j4 = '0')
    ELSE '1' WHEN (j1 = '0' and j2 = '0' and j3 = '0' and j4 = '1')
    ELSE '1' WHEN (j1 = '0' and j2 = '0' and j3 = '1' and j4 = '0')
    ELSE '1' WHEN (j1 = '0' and j2 = '1' and j3 = '0' and j4 = '0')
    ELSE '1' WHEN (j1 = '1' and j2 = '0' and j3 = '0' and j4 = '0')
    ELSE '0';
END SistemaArchitecture;

But I'm getting some many errors like:

  1. COMP96 ERROR COMP96_0015: "';' expected." "design.vhd" 24 8
  2. COMP96 ERROR COMP96_0019: "Keyword 'end' expected." "design.vhd" 24 8
  3. COMP96 ERROR COMP96_0016: "Design unit declaration expected." "design.vhd" 24 11

How I can do that?

Adson Henrique
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    What happens if `l3 => ` on line 24 becomes `l3 <= `? The parentheses aren't required here, a condition is bounded by reserved words. –  May 30 '20 at 17:01
  • OMG, I can't believe. I made exactly the change you said and it worked. Just `<=` instead `=>`. I didn't realize it, a thousand apologies for opening a topic just for a mere detail – Adson Henrique May 30 '20 at 18:18

1 Answers1

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As stated by the user1155120 the problem was in this:

What happens if l3 => on line 24 becomes l3 <= ? The parentheses aren't required here, a condition is bounded by reserved words.

I changed and works.

Adson Henrique
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