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I have an FPGA which accepts an 8-bit address and data bus (one bus is used for both) from two microcontrollers.

Using a 2:1 multiplexer, my FPGA only selects one device's inputs at a time (address and data) and the selection is based on an external signal to the FPGA.

I also have a separate decoder and register module which the microcontroller reads and writes to. How do I link the bidirectional output signal from my multiplexer to the decoder/register bidirectional input module at the higher level using the port map assignment?

Using a std_logic_vector(7..0), it will not work as I get an error "this signal is connected to multiple drivers". I think I need to tri-state the two, but I'm not sure. Looking at the image below, the green circle is what I'm trying to glue together.

My FPGA project

Enter image description here

Peter Mortensen
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g_ski
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    Your question shows a lack of a [mcve] (including the complete error message which would tell your reading audience what tool). Should you be referring to a synthesis tool there have only been a limited number of FPGA device families (Xilinx) with mapping tools accepting internal bidirectional net signal descriptions and these would be mapped into single directional nets. There's an underlying theme here, FPGAs don't support internal bidirectional nets (with more than one driver). See [ask]. –  May 29 '20 at 20:18

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You are right in thinking you need to tri-state, but this is needed at the edge of the FPGA, i.e., on the I/O pins.

You cannot have bidirectional ports inside an FPGA. So for each bidirectional pin you have three signals, incoming outgoing and a direction. If all pins always have the same direction you can use the same signal for all.

For you this means you don't need to multiplex the incoming signals as they can be split (one signal to multiple instances), but you need one for the outgoing signals (multiple instances to one signal).

Peter Mortensen
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