I'm now trying to implement pipeline CPU based on RV32I ISA.
My CPU has renaming algorithm for data hazards and branches prediction for control hazards.
This is my example code for renaming algorithm and branch prediction :
addi x1, x0, 25
addi x2, x0, 50
bne x1, x2, LABLE
addi x1, x0, 200
addi x2, x0, 300
LABLE:
addi x1, x1, 1
addi x2, x2, 1
Let me explains my CPU.
At line 1, "addi x1, x0, 25", x1's tag is 15.
At line 2, "addi x2, x0, 50", x2's tag is 14.
At line 3, "bne x1, x2, LABLE", the result of prediction is not taken. So, the instruction at line 4 is executed.
At line 4, "addi x1, x0, 200", x1's tag is 13. (This instruction should be not executed in true follow)
At line 5, "addi x2, x0, 300", x2's tag is 12. (This instruction should be not executed in true follow)
At line 6 and 7, these instructions need to read x1, x2 with the true tag is 15, 14, but in this case, the tags are read is 13, 12. So the CPU goes wrong.
So, when "bne" is done in the execute stage, How can it recover x1 and x2 tag to 15, 14 ?
What books or sources I should refer to resolve this problem ?