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Here is the code for the RAM module

module syncRAM( dataIn,dataOut,address,cs,we,oe,clk);

parameter ADR   = 8;
parameter DAT   = 8;
parameter DPTH  = 8;

input   [DAT-1:0]  dataIn;
output reg [DAT-1:0]  dataOut;
input   [ADR-1:0]  address;
input cs,we,clk,oe; 
reg [DAT-1:0] mem [DPTH-1:0];

always @ (posedge clk)
begin : MEM_READ
  if (cs && !we && oe) begin
     mem[address] = dataIn;
  end
end

always @ (posedge clk)
begin : MEM_WRITE
    if ( cs && we ) begin
         dataOut = mem[address];
    end
end

endmodule

Subhankar Ghosh
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  • Can you clarify what you mean by vertical and horizontal expansion? And please format your code correctly by indenting the whole think with 4 spaces or adding ``` at the start and end. – gatecat May 10 '20 at 07:04
  • can you show us what you have tried? it might clarify the question. – Serge May 10 '20 at 14:29

1 Answers1

1

I think what you are asking is a generic RAM code where you can modify Depth and Width of Memory. Here is a sample code, might not be up-to your specification

module RAM (

                ReadAddress  ,
                ReadEn       ,
                dataOut      ,

                WriteEn      ,
                WriteAddress ,
                dataIn       ,

                clk          ,
                rst_n                   
             );

parameter DAT  = 32           ;
parameter DPTH = 1024         ;
parameter ADR  = $clog2(DPTH) ; // 10

input      [ ADR  - 1 : 0 ] ReadAddress ;
input                      ReadEn       ;
output reg [ DAT  - 1 : 0 ] dataOut     ;

input                 WriteEn           ;
input [ ADR - 1 : 0 ] WriteAddress      ;
input [ DAT - 1 : 0 ] dataIn            ;

input clk                               ;
input rst_n                             ;

reg [ DAT - 1 : 0 ] ram [0 : DPTH-1] ; // DAT x DPTH = 32 x 1024

integer i ;

   always@( posedge clk )
      begin
         if ( !rst_n )
            begin
               dataOut  <= { DAT { 1'b0 } } ; 
            end
         else 
            begin     
               if ( WriteEn )                           // write
                  begin
                     ram [ WriteAddress ] <= dataIn  ; 
                  end

               if (ReadEn)                              // read
                  begin                                
                     dataOut <= ram [ ReadAddress   ] ;
                  end
            end

      end
endmodule

Here the parameters define the size of RAM module:

DAT is width of your data being written to and read from RAM.
DPTH is size or no of entries in your RAM.
ADR is size of Index used to traverse into RAM.

Here ADR is calculated according to the DPTH i.e. No of entries of RAM.
$clog2 is used to take log2() of DPTH and ceil it to the next integer value.

In current example $clog2(DPTH) is $clog2(1024) is equal to 10 the size od ADR

Thus ADR is used as size of Read and Write Address Signal.

By changing DAT and DPTH you can get RAM of any dimension.

I hope this is what you mean by Horizontal or Vertical Expansion

nincompoop_
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