I have been trying to use yosys in order to extract FSMs from my structural verilog file (gate library is simprims of Xilinx) with no success. I figured I might need to inform yosys which gate library I use or something similar, but as I said, no success. Is there anything I should do in order to make this work? Thank you.
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Can you add more details? Any code to share? – Thomas Weglinski May 09 '20 at 19:55
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Yosys' FSM extraction is designed to extract FSMs from coarse grain RTL-derived netlists. It is not going to be able to extract FSMs from technology-mapped netlists, this would need a different approach.
gatecat
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Thank you! Doesn't yosys support structural verilog at all? Is there anything I can do (maybe converting the design to a different format?) in order to use yosys' tools (fsm extraction, optimizations, etc)? or structural verilog files are just not supported? Thanks again! – sisack12345 May 06 '20 at 14:23
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Yosys supports structural Verilog. It is the FSM passes in Yosys that only work on directly RTL-derived netlists – gatecat May 06 '20 at 14:42
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I had no luck with optimizing the design through yosys, it couldn't even recognize I had muxes although I had. Except writing my design into other formats (such as AIGER, EDIF) I couldn't really do anything. – sisack12345 May 06 '20 at 17:01
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You might need to read in the cell definitions using read_liberty or read_verilog, followed by hierarchy and flatten – gatecat May 06 '20 at 17:29
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However, that will cause the original mapping to be lost, as it will replace cells with their implementations. – gatecat May 06 '20 at 17:30