I am trying to understand how makefiles work. This is a sample makefile:
all: prog
x.o: x.cpp globals.hh
$(CC) -c x.cpp
y.o: y.cpp globals.hh
$(CC) -c y.cpp
prog: x.o y.o
$(LD) -o prog x.o y.o -lc
If I do make file
and then make some changes in the x.cpp
, and then repeat make all
which commands are re-run?
From what I understand, the following commands will be re-run:
$(CC) -c x.cpp
and
-o prog x.o y.o -lc
And if I change the headers file instead, I think all three will re-run when I do make all again.
Am I correct? What would be the sequence?
Also, I am trying to understand how a dependency graph of a makefile could look like. I know that all, x.o, y.o and prog are targets here. But does my logic make sense?