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What HW feature does perf use to collect performance monitoring event for ring 0 on Intel CPUs?

My picture of the world is this:

  1. Looking for a free IA32_PERFEVTSELn MSR by asking IA32_PERF_GLOBAL_INUSE
  2. When taking a free IA32_PERFEVTSELn it sets the dedicated bit for a particular counter that is being programmed for the MSR as depicted in the Intel Documentation, Vol.3.

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Having said that either ring 0 or ring 3 or both are the only possible scenarios.

Some Name
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    Yes, the `OS` and `USR` bits are set as requested. Are you asking what the `perf` program is asking these bits to be set to? According to the manual you can specify suffix `:u` for user, `:k` for kernel or `:uk` for both. – Jester Apr 29 '20 at 19:13
  • @Jester Not really, I was actually interested in how those `:u` and `:k` worked under the hood. I mean I wanted to get a bit more details of the source of counters perf returns for kernel space code. – Some Name Apr 29 '20 at 19:51
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    They work by passing the flag to the kernel which then sets the bits in the register. Still not quite sure what you need but look in `linux/arch/x86/events/intel`. You can see stuff like `if (!event->attr.exclude_kernel) config |= ARCH_PERFMON_EVENTSEL_OS;` – Jester Apr 29 '20 at 20:07
  • @Jester Yes, [that's](https://elixir.bootlin.com/linux/v5.3/source/arch/x86/events/intel/bts.c#L229) exactly what I was looking for. – Some Name Apr 29 '20 at 21:28

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