-2

How to define a constant value for addition in verilog,

for example if I define a value A=64'h000000000000001;

use it later for addition how should I define in verilog.

dave_59
  • 39,096
  • 3
  • 24
  • 63
nikhil bellad
  • 1
  • 1
  • 3

1 Answers1

2

In SystemVerilog, it's reccomended that you put all constants in a global package, and import the package where needed

package globals;

  parameter A=64'h000000000000001;

endpackage
dave_59
  • 39,096
  • 3
  • 24
  • 63
  • Is it synthesisable and can I assign in this way .in any array a[0] ,a[1]........... – nikhil bellad Apr 19 '20 at 17:19
  • Yes, it's synthesizable. You must initialize a parameter is a single assignment, but the right hand side can be a concatenation to separate individual elements. `parameter bit [63:0] A = {1'b1, 1'b0, ... );` – dave_59 Apr 19 '20 at 17:55