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I am implementing a 2:1 MUX using AND, OR, NOT, etc with fault handling but there is a problem in the code, I haven't done this complex code earlier. I wanted to make a module through which I can see the change in output when I inject a fault to any node. I didn't find the error so can anyone help me.

I have attached the code and Screenshot of the output run in the command prompt.

module Inverter (in, out, fault);
    input in, fault;
    output out;
    assign out = fault ? in : ~in;
endmodule

module LShapedWire(in, out, fault);
    input in, fault;
    output out;
assign out =  fault ? ~in : in;
endmodule

module Fanout(in, out1, out2, fault1 fault2);
    input in, fault1,fault2;
    output out1, out2;
    assign out1 = fault1 ? ~in : in;
    assign out2 = fault2 ? ~in : in;
endmodule

module And (input1 , input2 , out2, fault)
    input input1, input2, fault;
    output out2 , out1;
    assign out1 = input1 & input2;
    assign out2 = fault ? ~out1 : out1;
endmodule

module Or (input1 , input2 , out2, fault)
    input input1,input2 ,fault;
    output out1, out2;
    assign out1 = input1 | input2;
    assign out2 = fault ? ~out1 : out1;
endmodule

module mux:

reg A , B , Sel;
reg faultLS1 , faultLS2;
reg faultAND1 , faultAND2;
reg faultINV1;
reg faultOR1;
reg fault1FO1, fault2FO1;

wire outAND1 , outAND2;
wire outLS1 , outLS2;
wire outINV1;
wire outOR1;
wire out1FO1 , out2FO1;


initial
begin
A=0;B=0;Sel=0;
faultLS1 = 0; faultLS2 = 0;
faultAND1 = 0; faultAND2 = 0;
faultINV1 = 0;
faultOR1 = 0;
fault1FO1 = 0; fault2FO1 = 0;
#10 B=0;Sel=1;
#10 B=1;Sel=0;
#10 Sel=1;
#10 A=1;B=0;Sel=0; 
#10 B=0;Sel=1;
#10 B=1;Sel=0;
#10 Sel=1;
end

Fanout FO1(Sel, out1FO1 , out2FO1 , fault1FO1, fault2FO1);
LShapedWire LS1(out1FO1, outLS1, faultLS1);
And AND1(A , outLS1 , outAND1 , faultAND1);
Inverter INV1(out2FO1 , outINV1 , faultINV1);
And AND2(outINV1, B , outAND2, faultAND2);
LShapedWire LS2( outAND2 , outLS2 , faultLS2);
Or OR1(outAND1 , outLS2 ,outOR1 , faultOR1);

initial
begin
$monitor($time,,,,,Sel,,A,,B,,,,,,outOR1);
end
endmodule

Screenshot of error message

toolic
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Ashking007
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1 Answers1

0

fault1 fault2 comma missing.

out2 , out1; there is no out1.

Oldfart
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  • I have corrected comma, is it possible in AND and OR module to not add out1 and still get output because my final output is out2. Plz help – Ashking007 Apr 11 '20 at 14:24