Here is my Makefile:
.PHONY: test%
test1:
# jobserver is UNavailable
make -C sub
test2:
# jobserver is available, ok
+make -C sub
test3:
# jobserver is available, ok
$(MAKE) -C sub
test4:
# jobserver is available, ok
+$(MAKE) -C sub
sub
is sub-directory that contains another Makefile (sub-make).
When I run test1
rule:
$ make -j8 test1
make -C sub
make[1]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule.
I get warning that jobserver is unavailable and sub/Makefile
is really run in single thread (as if -j1
).
They say I should add +
and so I run a test2
target which contains +
before make
command. And now I don't see the warning and sub/Makefile
is really run in parallel. But according to this answer, the +
sign is not for running in parallel but for forcing running commands even if make
is run with -n
, -t
, -q
flags. But why does +
enables jobserver?
When I run test3
target that doesn't use +
but uses $(MAKE)
for running sub/Makefile
, it doesn't give jobserver warning as well (parallel execution works). So what is difference between make
and $(MAKE)
? I thought it is just for allowing to substitute default make with user-defined make. When I don't override MAKE
variable, I see the same make
command as I see in the test1
target. But why does the $(MAKE)
enables jobserver and make
does not?
Running test4
target does not give jobserver warning also (works in parallel).
Please note my question is different from this one. It is about cmake, my question is about make. There is also related question, but it doesn't answer my questions.