1

In MIPS, all other instructions (aside from sw) seem to have the destination operand before the source(s). Why is it that sw seems to be the only instruction to violate this? Is it due to the hardware in some way?

Edit: This seems to apply to all save instructions (sw, sb, and sh) according to this reference sheet. Any ideas?

jdub
  • 170
  • 10
  • Every instruction that takes a memory operand has that operand appear last in order. I don't know if it says anywhere in the official documentation why they went with that coinvention, but note that this isn't unique to MIPS (e.g. ARM has the memory operand last for both `ldr` and `str`). – Michael Mar 05 '20 at 21:08
  • It's basically just convention; an answer on the linked duplicate makes an argument that it makes sense based on the I-type instruction format that both load and store instructions use. (RISC-V is different from MIPS, but the design philosophy is very similar. The fields are in different places / different widths, but everything else applies.) – Peter Cordes Mar 05 '20 at 21:09
  • 1
    not related to hardware in any way shape or form, assembly language is arbitrary it only needs to convey enough information to create the machine code. for each ISA you can have as many completely different syntaxes/solutions as there are people willing to create one. – old_timer Mar 05 '20 at 21:09
  • 1
    From a micro-architectural point of view, `sw` has two source register operands, and no register target. – Erik Eidt Mar 05 '20 at 21:20

0 Answers0