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Early on, memory size was little (64 KiB) and it just needed a 16-bit register to address it. But later memory with 1 MiB came. So we need bigger address registers. But in 8086 CPUs instead they used another register and called it offset.

So with 16-bit main register we can address 65536 segments and with 16-bit offset we can address 65536 bytes in those segments so the whole memory that we can address should be 65536 * 65536, that means 4 GiB that we can address.

But on an 8086 we can address 1 MiB with a 32-bit far pointer (16-bit segment + 16-bit offset). Why is that?

Peter Cordes
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  • The segments overlap! – Nate Eldredge Feb 29 '20 at 14:30
  • u mean we can adress one bit in many way. it mean we can addrss a bit in 3855 ways –  Feb 29 '20 at 14:48
  • In 4096 ways, actually. (You seem to have a lot of numerical and other typos in your question.) For example, the seg:ofs addresses `12AB:34CD` and `12AC:34BD` both refer to the same byte, at linear address `15F7D`. – Nate Eldredge Feb 29 '20 at 15:36

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As mentioned in the comments by Nate Eldredge, the segments overlap. Each subsequent 86 Mode segment starts 16 bytes after the prior one. So (as mentioned) there are 4096 (4 Ki) ways to address any one byte.

The exception is to do with A20 handling on later x86 CPUs. On those, if A20 is enabled, memory in the first 64 KiB has less aliases pointing to it. An address that would "wrap" on the 8086, starting with 0FFFFh:0010h, would have pointed into the first 64 KiB (starting with linear address 00_0000h).

If A20 is enabled, the high addresses do not "wrap" any longer, so that 0FFFFh:0010h actually refers to the linear address 10_0000h (exactly at 1 MiB = 1_048_576 Bytes). The highest accessible address in Real or Virtual 86 mode with A20 enabled is 0FFFFh:0FFFFh, which points to linear 10_FFEFh (just below 1088 KiB - 16 Bytes), that is 1_114_096 Bytes are addressable using a 16:16 far address.

Michael Petch
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ecm
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    Since you bring up v8086 mode. If you aren't using paging then there would be no wrap and you'd be accessing linear addresses about 1MiB (assuming A20 is enabled!). However when paging is enabled the 64Kib just above 1MiB can be mapped to the first 64KiB of address space to simulate the appearance of A20 being disabled. Some v8086 software allowed simulating no A20 this way. I think Quarterdeck/Desqview had such an option. I had already upvoted before commenting – Michael Petch Feb 29 '20 at 19:33
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    @Michael Petch: While that is true, this compatibility feature just simulates A20 being disabled with the MMU, that is, the translation of linear to physical addressses. The HMA addresses still compute to *linear* addresses above 1 MiB then. These linear addresses are just mapped to the same physical addresses as the first 64 KiB. Arguably, on the actual 8086 the linear address wraps around too, though it can be considered that it didn't have an MMU so linear and physical were the same. – ecm Feb 29 '20 at 19:44