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If cpu word size is 32 bit, that is it can process 32 bit in one go. And ,the size of a single memory cell in RAM is 64 bit. So , Data bus has to be 32 bit , due to processor word size.

How will then the whole data of a memory cell be read by cpu?

Narender
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  • What do you mean by "memory cell"? Normally that means either one bit (https://en.wikipedia.org/wiki/Memory_cell_(computing)), or the smallest addressable unit of memory. Do you mean you have a 64-bit ISA (with 64-bit registers) and a CPU where normal 64-bit instructions decode to 2x 32-bit halves of a 64-bit operation? – Peter Cordes Feb 26 '20 at 23:39
  • @PeterCordes thanks for the response. I meant, smallest addressable unit of main memory, is 64 bit, and CPU which has 32 bit registers, 32 bit data bus from memory. So now, if one single memory address stores 64 bit data, and cpu can read 32 bit at a time with data bus, how would it access the whole 64 bit , in this situation? – Narender Mar 03 '20 at 18:48
  • All modern 64-bit CPUs have "byte-addressable" memory (google that term). I've never heard of a word-addressable machine with 64-bit words. Even Alpha was sort of byte addressable but didn't have 8 or 16-bit load/store instructions, but did have both 32 and 64-bit load/store instructions. Also your premise doesn't even make sense, as well as not being how real CPUs work. Unless you're talking about a system with cache that only does large-burst transfers to/from DRAM, but actual loads/stores and instruction fetches happen in narrower chunks from cache. – Peter Cordes Mar 03 '20 at 18:53
  • yeah, this kind of machine doesnt work, thats what I wanted to hear. Thanks.(just a beginner, pardon me for a question that din't even make sense, but I thought there might be some way for this to work). – Narender Mar 04 '20 at 14:29

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