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describe how a JTAG connection is used to test the circuitry in a chip using just 5 pins

MignolaFan
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  • It's a technique called boundary scan - google it. All the I/O and test points in the chip are wired through a chain of shift registers. The actual test is done using just 2 pins one as input into the shift registers and another as output. All other pins just supports these two pins - clocking, enabling JTAG etc. You shift in your test pattern, one bit at a time (just one pin), perform your test (advance chip clock, trigger chip event.. whatever that needs to be done) then shift your test result out one bit at a time (just one pin - the other pin) – slebetman Feb 16 '20 at 07:58
  • JTAG input pin can be chained with another chip's output pin so JTAG can not only test a single chip with 5 pins, it can test an entire system - PCB, multiple PCBs on a motherboard, entire rack of computers etc. with the same 5 pins but your test tool needs to know about how the chips are chained together – slebetman Feb 16 '20 at 08:00
  • https://en.wikipedia.org/wiki/Boundary_scan – slebetman Feb 16 '20 at 08:01
  • If anyone wants to compile this into an answer feel free to do so. I just think this is easily googleable once you know the correct terminology – slebetman Feb 16 '20 at 08:02

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JTAG is used as a synonyme for the boundary scan protocol, see - https://en.wikipedia.org/wiki/JTAG#Boundary_scan_testing - https://en.wikipedia.org/wiki/Boundary_scan It was the Joint Test Action Group (JTAG) who originally devised this protocol for testing circuitry around chips.

Besides this original purpose, the same protocol is used to program and debug CPUs, FPGAs etc.

In order to use JTAG, you need an adapter device that supports the circuitry you would like to test/debug.

[...] using just 5 pins

You are wondering how to test the entire chip through "just" 5 pins? To get a rough idea, think of a shift register similar to UART and SPI (but keep in mind that JTAG is notably more sophisticated).

HelpingHand
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