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Hello I am trying to implement an operating system for x86. In protected mode it is said that there are a total of 256 interrupt service routines that can be defined in interrupt descriptor table IDT. I cannot understand why there are so many entries while there are only 15 IRQ lines available. What is the relation between only 15 IRQ lines and 256 ISRs? I mean how they are mapped?

Peter Cordes
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WhiteFlowers
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    Because you can generate a *software* interrupt with the `int xxh` exception. Also note that: 32 vectors are reserved for exceptions. The IRQs are more than 16, 16 are the legacy ones, but the IOAPIC supports more (mine, for example, has more than 100 IRQ lines) and the IPI and MSI (both kinds of interrupts) can have arbitrary vectors. That said, yes, 256 are probably more than ever needed. I think it's just due to using 1 byte for specifying the vector (easier than clipping or using weird widths). – Margaret Bloom Feb 08 '20 at 17:20
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    @Margaret, modern server systems use more than 224 interrupts. They have NIC and storage devices that generate a separate interrupt for each queue. MSI-X supports up to 2048 interrupts per device. To do this, the OS has to have a separate IDT for each core. The interrupt remapping table routes each interrupt to the right core, with a vector number specific to that core. – prl Feb 08 '20 at 21:37
  • @prl Good point about servers, I haven't seen many of them. – Margaret Bloom Feb 09 '20 at 07:52

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