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I am learning my way through smth32f746ng microcontroller, and ran in to few questions regarding flash and writing to flash with OpenOcd.

So opoenOCD writes by default to first bank of flash at adress 0x0. Processor can access flash via ITCM bus or AXIM with adresses of 0x08000000(Itcm) or 0x00200000(Axim). As i assume, when process reads instruction from lets say 0x08000000 via ITCM bus it therefore reads 0x0 flash address.

The question is: When processor boots up, what register controlls the intial way of fetching the first instruction. Will it fetch using ITCM or AXIM bus?

If anyone could point me tot he right place in docs would be awesome.

Anton Stafeyev
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1 Answers1

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You setup the vector table and the address at offset 0x004 in that table is the reset vector which determines where it fetches the first instruction. So its up to you which one.

the ARM docs tell you how the vector table works. that address 0x00000004 in the arm address space is the reset vector. the ST docs tell you what 0x00000004 maps to depending on the boot0 pin (and maybe boot1 if present). the ST doc tells you that 0x00200000 and 0x08000000 point at ITCM and AXIM paths to the user/application flash.

So the read of 0x00000004 to determine the reset vector may go through one of the busses all the time, after that it is what you put in offset 0x004 of the vector table that determines what bus the first instruction is fetched through. And the rest of your code determines where the rest of the instructions are fetched from/through.

old_timer
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  • yeah but it needs to read the flash to actually fetch address that is stored at 0x004, thats the point, the vector table i learned from your previous answer :) idid my homework, the reason i asked is maybe there is some fuse bits to set up to actually tell it to use itcm or axim. kinda weird that it is in kind of undefined state. – Anton Stafeyev Feb 08 '20 at 19:22
  • the st docs cover what the busses are tied to this is an st chip not an arm chip (arm doesnt make chips) the st docs say what is mapped to address 0x00000000 – old_timer Feb 08 '20 at 20:04
  • okay found it in a few seconds, this part doesnt use a boot0/boot1 pin it has a non-volatile register that determines what 0x00000000 maps to. factory setting is 0x00200000 depending on another bit/register, so you are right this is a register not a strap pin like the large majority of the stm32 parts I am used to. – old_timer Feb 08 '20 at 20:07
  • they are moving away from the built in bootloader thing it appears, will see if they standardize on a new solution. – old_timer Feb 08 '20 at 20:09
  • "In the STM32F76xxx and STM32F77xxx, two different boot areas can be selected through the BOOT pin" there is a pin – old_timer Feb 08 '20 at 20:11
  • this part has a lot more choices than prior parts – old_timer Feb 08 '20 at 20:13
  • i am still missing some vocab to actually search docs for some of the tearms and concepts :) – Anton Stafeyev Feb 09 '20 at 10:37
  • Ok, found it :) the default fetch will be forced from the Flash memory on ITCM interface at the address 0x00200000 if BOOT_ADD0 or BOOT_ADD1 out of range. so ITCM will be the default, and it is possible to boot from RAM, that wahat iw as looking for initially :) – Anton Stafeyev Feb 09 '20 at 11:50
  • Let us [continue this discussion in chat](https://chat.stackoverflow.com/rooms/207496/discussion-between-anton-stafeyev-and-old-timer). – Anton Stafeyev Feb 09 '20 at 13:42