From man 2 syscall:
The first table lists the instruction used to transition to kernel mode
(which might not be the fastest or best way to transi‐
tion to the kernel, so you might have to refer to vdso(7)), the register used to indicate
the system call number, the register
used to return the system call result, and the register used to signal an error.
arch/ABI instruction syscall # retval error Notes
────────────────────────────────────────────────────────────────────
...
sparc/32 t 0x10 g1 o0 psr/csr [1]
sparc/64 t 0x6d g1 o0 psr/csr [1]
...
When I review samples of assembly performing syscalls on SPARC, I see two different methods to transition into the kernel:
t 0x10(as suggested from the man pages)ta 8
Two random examples:
- https://linuxsecurity.com/resource_files/documentation/virus-writing-HOWTO/_html/sparc-debian2.2-linux/language.of.evil.html
- https://unix4lyfe.org/hello-sparc/
However, I don't see the t instruction anywhere in SPARC Architecture manual. Instead I see a family of trap instructions (the Ticc instructions), which includes the "trap always" ta instruction.
From the SPARC manual (https://www.gaisler.com/doc/sparcv8.pdf):
A Ticc instruction evaluates the integer condition codes (icc) according to
the cond field of the instruction, producing either a “true” or “false” result.
If “true” and no higher priority exceptions or interrupt requests are pending,
then a trap_instruction trap is generated. If “false”, a trap_instruction trap
does not occur and the instruction behaves like a NOP.
If a trap_instruction trap is generated, the tt field of the Trap Base Register
(TBR) is written with 128 plus the least significant seven bits of “r[rs1] +
r[rs2]” if the i field is zero, or 128 plus the least significant seven bits of
“r[rs1] + sign_ext(software_trap#)” if the i field is one.
After a taken Ticc, the processor enters supervisor mode, disables traps,
decrements the CWP (modulo NWINDOWS), and saves PC and nPC into
r[17] and r[18] (local registers 1 and 2) of the new window. See Chapter 7,
“Traps.”
I'm trying to understand which entry of the TBR is used by each version of these syscalls. Since all the software traps are at 0x80 -- 0xFF, it must be one of those. There are two rules outlined in the Ticc family:
- 128 plus the least significant seven bits of “r[rs1] + r[rs2]” if the i field is zero
- 128 plus the least significant seven bits of “r[rs1] + sign_ext(software_trap#)” if the i field is one
Can anyone explain the difference between t 0x10 and ta 8? In particular, can you explain which of those rules is applied and the value of the TBR offset being used in each case?
