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I have a makefile that is to be built by [Microsoft] nmake. It references another file as an include. I do not get to modify the included file. The problem is that one of the user-defined macros used by both isn't quite right for use by the include. How can I redefine this macro ONLY for where it's used in the include?

I tried something like:

`B=$(A)

A=$(C)

!include myfile.make

A=$(B)`

nmake, however did not like this. Is there another way to do this?

nuit9
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1 Answers1

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I just ran a test case, and the behavior I got does not agree with your description.

Suppose I have two makefiles, ...

nuit.mak: 

A=17

!include nuit-a.mak

A=5

all: child main

main:
    @echo A = $(A)

And nuit-a.mak: 

child:
    @echo A = $(A)

Here are the results I see: 

c:\dev\make>nmake -f nuit.mak main

A = 5

c:\dev\make>nmake -f nuit.mak child

A = 17

c:\dev\make>nmake -f nuit.mak all

A = 17
A = 5
Cheeso
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  • I think the problem is coming from not using constants. The error I was getting is around 'cyclic' definitions. – nuit9 May 15 '11 at 03:18