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I think this question is best understood with an example. So here we go:

Imagine the following are defined:

parameter number_of_points_before_point_of_interest = 4;

logic [15:0] test_data = 16'b0000111100001111;
logic [3: 0] point_of_interest;
logic [7: 0] output_data;

if the value assigned to point_of_interest is 1 and the value to number_of_points_before_point_of_interest is 4. I want my output_data to be {test_data[E: F], test_data[5:0]} or 8'b00111100.

So in essence, I want to take 8 bits starting from (point_of_interest - number_of_points_before_point_of_interest) and ending at (point_of_interest - number_of_points_before_point_of_interest + 7).

Since point_of_interest is a variable number, the following two indexing methods are invalid:

To make the code more concise: point_of_interest --> pot

number_of_points_before_point_of_interest --> num_pt_before_pot

buffer[pot - num_pt_before_pot: 4'hF]  // Invalid since pot not constant
buffer[pot -: num_pt_before_pot]       // Part-select doesn't work either

Note: Variability of pot is not an issue in the second case since starting point can be variable. Regardless, part-select does not provide the desirable results in this example.

Your help is very much appreciated. Thanks in advance

Mas
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  • in the second case, 'num_pt_before_port' must be a constant. 'pot' can be a variable. – Serge Jan 31 '20 at 19:46
  • Yup, that's true. However, part-select doesn't work when you want to wrap around the buffer. I'll edit to indicate this. – Mas Jan 31 '20 at 19:55
  • in system verilog the **width** of a part select must be a *constant*. (there are no variable-sized wire bundles in hardware). If you cannot make it a constant, you cannot use this part select. Try a different approach with single elements (width == 1). – Serge Jan 31 '20 at 21:40

1 Answers1

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A simple trick you can do is replicate your test_data, then take a slice of it

  output_data   = {2{test_data}}[16+pot-before_pot-:2*before_pot];
dave_59
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