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Is it posible to make array of unconstrained array in vhdl? I am using XCELIUM 18.03-s001.

This is how I declare signal type in pkg_test.vhd:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package pkg_test is

   type t_data_bus_array is array(natural range <>) of std_logic_vector;

end pkg_test;

This is entity test_entity.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.pkg_test.all;

    entity test_entity is

   generic (
      DATA_WIDTH       : natural := 9;    -- Data width of single input
      NUMBER_OF_INPUTS : natural := 4     -- Number of inputs
   );

   port 
   (  

      pi_data         : in  t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0);

      po_data         : out  t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0)

   );
end test_entity;

architecture test_entity_behav of test_entity is

begin

   po_data <= pi_data;

end test_entity_behav;

And this is my error.

[saka@serbia workspace]$ xrun -top test_entity -f filelist -elaborate -clean -sv -access +rwc -v200x
xrun: 18.03-s001: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
xrun: *N,CLEAN: Removing existing directory ./xcelium.d.
pkg_test.vhd:
    errors: 0, warnings: 0
test_entity.vhd:
      pi_data         : in  t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0);
                                                                         |
xmvhdl_p: *E,MISRPN (test_entity.vhd,42|73): expecting a right parenthesis (')') [1.1.1].
      pi_data         : in  t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0);
                                                                                    |
xmvhdl_p: *E,MISCOL (test_entity.vhd,42|84): expecting a colon (':') 87[4.3.3] 93[4.3.2].
      pi_data         : in  t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0)(DATA_WIDTH-1 downto 0);
                                                                                                  |
xmvhdl_p: *E,EXPEND (test_entity.vhd,42|98): expecting the reserved word 'END' [1.1].
end test_entity;
|
xmvhdl_p: *E,EXPACE (test_entity.vhd,47|0): expecting a library unit [11.1].
architecture test_entity_behav of test_entity is
                                            |
xmvhdl_p: *E,ENNOFN (test_entity.vhd,49|44): Intermediate file for entity 'TEST_ENTITY' could not be loaded, entity may require re-analysis.
    errors: 5, warnings: 0
xrun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting.

It is obviously, that I make some mistake

If I use this declaration

type t_data_bus_array is array(natural range <>) of std_logic_vector(DATA_WIDTH-1 downto 0);

and in entity like this

pi_data         : in  t_data_bus_array(NUMBER_OF_INPUTS-1 downto 0);

There is no error.

SakaSerbia
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    It is possible to use a unconstrained array in VHDL-2008. Saying that, your errors may be due to something else. A [mcve] is needed to look into this, – maximus Jan 22 '20 at 12:14
  • Only error is how I use unconstrained array or my tool is not compile VHDL-2008. – SakaSerbia Jan 22 '20 at 12:18
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    The way you use is correct. So tool might not be supporting VHDL-2008 (or you need to enable it). – maximus Jan 22 '20 at 12:36
  • How to enable this? I write xrun -helpsubject vhdl but there is no comand to enable this. – SakaSerbia Jan 22 '20 at 12:41
  • I never used Cadence tool. In Modelsim, the command line option is -2008. I believe there will be something similar to it if it supports. – maximus Jan 22 '20 at 13:18
  • I found only -v200x // All VHDL source files are parsed with VHDL 2000, but from some reason there is still error. – SakaSerbia Jan 22 '20 at 13:20
  • Let us [continue this discussion in chat](https://chat.stackoverflow.com/rooms/206447/discussion-between-rakend-and-sakaserbia). – maximus Jan 22 '20 at 13:21
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    The question title is not correct. Type t_data_bus_array is not a two-dimensional array type. IEEE Std 1076-2008 5.3.2.1 "An array object is characterized by the number of indices (the dimensionality of the array); ..." where your type has one index and has an element type which is also a single-dimensional array type and. There can be advantages, an object of a single-dimensional array type can be sliced. (8.1). `po _data` is not a valid identifier (6.5.2 Interface object declarations, 15.4.1). –  Jan 22 '20 at 19:36
  • @user1155120 1076-2008 - IEEE Standard VHDL Language is superseded. So only actibe standards is 1076-2019 - IEEE Standard for VHDL Language and 1076-2002 - IEEE Standard VHDL Language – SakaSerbia Jan 23 '20 at 08:38
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    There are no VHDL implementations conforming to -2019 (which was published on the 23rd of December). The definition of dimensionally has not changed. –  Jan 23 '20 at 09:36

1 Answers1

1

If you are not using the VHDL2008 the unconstrained arrays of std_logic_vector are not supported.

You could define a vector array of std_logic type like this:

type SlVectorArray is array (natural range<>, natural range<>) of std_logic;
  • I was think on that but if I write this next_chunk <= pi_data (po_sel_mux, DATA_WIDTH-1 downto 0); I get error. It is not elegnt to make for loop for this, and I have staff like this on a lot of place in my code. xmvhdl_p: *E,ILLRNG (test_2.vhd,183|62): range is not allowed here [6.1] [6.5]. errors: 1, warnings: 0 – SakaSerbia Jan 24 '20 at 13:31
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    `next_chunk <= pi_data (po_sel_mux, DATA_WIDTH-1 downto 0);` doesn't show up in the question code, the new object declarations aren't known here. It fails because only a single dimensional array type (e.g. pkg_test type t_data_bus_array) can be sliced (IEEE Std 1076-2008 8.5 Slice names). While uroš legat can't provide a solution to a problem not present in the example it's possible to hide the *not elegant* for loop by [providing a type converting subprogram in the package](https://i.stack.imgur.com/A8Z70.jpg) used to provide the type declaration for ports. –  Jan 24 '20 at 18:49