I am trying to implement a FIFO buffer with 4 positions . I have tried an implementation using the concept of FSM . The diagram consists of 5 states :
Empty , Write , Read , Full , Wait(to avoid some race conditions).
It turned out to be harder than I expected . Is it advisable to use FSM for a cirquit like this or stick with traditional sequential logic ? When is it worth to design with FSM ? I know this is more of a theoretical question rather than a code problem , but It's something that I can't find a definite answer .