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I am trying to implement a FIFO buffer with 4 positions . I have tried an implementation using the concept of FSM . The diagram consists of 5 states :

Empty , Write , Read , Full , Wait(to avoid some race conditions).

It turned out to be harder than I expected . Is it advisable to use FSM for a cirquit like this or stick with traditional sequential logic ? When is it worth to design with FSM ? I know this is more of a theoretical question rather than a code problem , but It's something that I can't find a definite answer .

Atheros
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    Your question is a little vague. FIFOs are usually a ram that can be written and read at the same time, and you wouldnt usually use a FSM. Just read and write pointers. – Tricky Dec 14 '19 at 16:20
  • Why do you think you need a wait? None of my FIFOs ever had one. (Humm, they did not have an FSM either so....) – Oldfart Dec 14 '19 at 16:55
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    "A _Finite State Machine_ is any device storing the state of something at a given time. The state will change based on inputs, providing the resulting output for the implemented changes." A FIFO in hardware always involves more than one FSM. Your debate is over the number and their relative complexity and as Oldfart's comment demonstrates the nomenclature used in describing them. Your 'One FSM to bnd them all can't be exposed to opinion (however expert) here without presenting a specific problem. Provide a [mcve]. –  Dec 14 '19 at 20:53

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An FSM remembers states between clock cycles. In a FIFO you don't need that.

You either read in one clock cycle or you write one clock cycle (Or if you have dual-ported memory you can do both at the same time.)

Whatever you do, the operation has finished after one clock cycle. There is no 'state' to remember*.

*The data in the FIFO memory can have changed , but you don't call a memory an FSM either.

Oldfart
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  • Yes, @Harry I saw the down vote and I assumed it was the op who thinks that full/empty must be states while in reality they are derived from the read/write pointers. Wait until whoever downvoted tries to make an asynchronous (dual-clocked) FIFO in one state machine.... – Oldfart Dec 31 '19 at 11:05