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I want to periodically check the state of the RAM ECC detection in my firmware on a STM32H753.

The ECC mechanism is well described in the Reference Manual for the Flash but not very well (in my opinion) for the RAM.

I've seen that there are dedicated interrupts for RAM ECC but it is not clear if they are triggered for single error or double error ?

Also, why a dedicated interrupt and not a BusFault (like it is done on the Flash if I understood correctly ?)

Also , I don't want to get interrupted for a single error (that is properly corrected). Instead I want to get the status periodically and log the error somewhere. What is the register to read to check whether a single error happened ?

Guillaume Petitjean
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I've got an answer on STMicro forum, I thought it might be helpful to post it here. The answer is from a member called Berendi.

"RAMECC status and interrupt flags are defined in the stm32h7??xx.h headers, and there are some code examples in stm32h7xx_hal_ramecc.h/.c Apparently it's possible to independently mask single/double ecc fault interrupts. There is application note AN5342 as well, but it's not very helpful."

Guillaume Petitjean
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