I am building a custom full system configuration (largely influenced by ARM in configs/FSConfig.py) and am running into an issue where the kernel hangs on boot, being unable to access the disk image to mount the root filesystem. Looking at the kernel boot logs and gem5 call trace, I strongly suspect the culprit has to do with this:
[ 0.000005] ata_piix 0000:00:01.0: BMDMA: BAR4 is zero, falling back to PIO
In other words, while a standard ARM FS mode simulation will enable bus mastering on the simulated gem5 (PIIX) IDE controller and use DMA to access the disk, my simulation reverts to PIO instead. The PCI node of my device tree is the one from ARM’s vexpress (aarch64) dtb. My PCI host/IDE controller setup is also similar to ARM’s setup:
self.cf0 = CowIdeDisk(driveID='master')
self.cf0.childImage(mdesc.disk())
self.pci_host = GenericPciHost(conf_base=0x30000000, conf_size=’256MB’, confi_device_bits=12, pci_pio_base=0x2f000000)
self.pci_ide = IdeController(disks=[self.cf0], pci_dev=1, pci_bus=0)
pci_devices.append(self.pci_ide)
…
self.pci_host.pio = self.iobus.master
for dev_id, dev in enumerate(pci_devices):
dev.host = self.pci_host
dev.pio = self.iobus.master
dev.dma = self.iobus.slave
The gem5 call trace includes the following (no methods from CowDiskImage are called):
IdeController::Channel::accessCommand: offset = 6, size = 1, read = 0
IdeDisk::updateState: action = 4.
IdeDisk::writeCommand: Write to disk at offset: 0x6 data 0xa0
IdeController::dispatchAccess: Write from offset: 0x2f000016 size: 0x1 data: 0xa0
IdeDisk::readControl: Read to disk at offset: 0x2 data 0x40
IdeController::dispatchAccess: Read from offset: 0x2f000022 size: 0x1 data: 0x40
IdeDisk::writeControl: Write to disk at offset: 0x2 data 0xa
IdeController::dispatchAccess: Write from offset: 0x2f000022 size: 0x1 data: 0xa
I have already verified that my kernel includes drivers for the PIIX, legacy ATA controllers, and BMDMA. I have also attempted to change the BAR4 value of the IDE controller directly in the system configuration file and update the device tree with a dma-ranges field for the PCI node. None of these solutions worked.
TL;DR: How do I ensure that my full system configuration supports and enables bus mastering for the IDE controller? Is there anything special I need to add to the device tree binary?
