i know it uses physical address = segment register << 4 + offset register. Although these two registers are 16-bits, how can 8086 handle a 20-bit plus operation?
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The Bus Interface Unit consists of segment registers, adder to generate 20 bit address and instruction prefetch queue. Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and they fill a First In First Out 6 byte queue.
See a document called "8086_Internal_Block_diagram_enotes.pdf", easily to be found via Google. Also see this document, the section about the Bus Interface Unit.
So the processor generates these 20-bit addresses "on demand" with a dedicated internal 20-bit register, if you will.
DarkDust
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1I see,thanks! so essentially the address calculation does not use the traditional 16-bit ALU(?) – Oxdeadbeef May 04 '11 at 08:19
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1@0xdeadbeef: Correct, it has its own dedicated "mini-ALU" in the BIU. – DarkDust May 04 '11 at 08:31
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When you shift a 16 bit number 4 places to the left, you're essentially creating a 20 bit number. The offset then indicates how far into that range you will go. See the Wikipedia article on Real mode addressing.
Example:
0x0001 << 4 -> 0x00010 (5 sets of 4 bits in each hex digit -> 20 bits)
jonsca
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I guess the question was more along this: since all registers are 16-bit, how can the processor handle a 20-bit value which is too big for a normal register. – DarkDust May 04 '11 at 08:10
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@DarkDust Yes, that's how I interpreted it too. Yours is more complete, I was just trying to address the question directly. – jonsca May 04 '11 at 08:12