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Would someone explain me the difference between dispatch,commit,issue and squash width in a cpu core, which executes in an out of order fashion.

From what I know:

  • issue width - how many instructions that can execute in parallel
  • dispatch width - how many instructions that can be inside the reorder buffer(not sure)

and I have no idea of the other two. An explanation would be helpful

Peter Cordes
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Weez Khan
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  • "squash width"? Are you sure that's a real thing? Squashing instructions (discarding instructions from the wrong path of a mispredicted branch for example, and not writing back their results into the architectural state) is totally a thing, but it doesn't typically have a limited width. – Peter Cordes Nov 04 '19 at 12:00
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    Most of these terms become clear from context (or even defined outright) if you read something like http://www.lighterra.com/papers/modernmicroprocessors/ (which is very good and you should read it anyway if you haven't). Also things like https://www.realworldtech.com/sandy-bridge/ (David Kanter's deep-dive on that Intel microarchitecture), or Agner Fog's microarch pdf (again x86 microarchitectures) explaining issue into the ROB and commit = retire from the ROB. https://agner.org/optimize/ – Peter Cordes Nov 04 '19 at 12:03
  • @PeterCordes, squash width, is a parameter for an out of order cpu that I am trying to model in gem5. And the "squash"parameter is defined as a width with a default value of 8. – Weez Khan Nov 04 '19 at 12:27
  • Ok, that gem5 context is important. Intel terminology uses "dispatch" and "issue" opposite from many other computer-architecture people / textbooks. One is number of instructions that can be renamed and added to the ROB + scheduler in a cycle, the other is the number that can be sent to execution ports from the scheduler in a cycle. (In x86 CPUs, micro-fusion of load+ALU (memory-source x86 instructions) means that issue width is measured in fused-domain uops but dispatch width is measured in the unfused domain.) – Peter Cordes Nov 04 '19 at 12:40
  • It seems GEM5 uses the non-Intel convention, so dispatch = rename limit (not ROB *size*) – Peter Cordes Nov 04 '19 at 12:40

1 Answers1

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  1. Issue Width: How many instructions can be pushed by decode into execute (EX) stage. Typically limited by size of issue queue (IQ) (in EX, instructions are first pushed into IQ and then "dispatched" to ALUs/Functional-Units for "real" execution)

  2. Dispatch Width: How many instructions can move from IQ to ALUs/FUs. Limited by the number of ALUs/FUs, or how much of the IQ we read/cycle.

  3. Commit/Squash Width: How many instructions are committed/squashed per cycle. GEM5 seems to be modelling bandwidth requirements that are associated with commit/squash per cycle (typically it involves removing entries from ROB and adjusting rename tables)

instinct71
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